And what about testing a Stateflow Model only? Is there also a deviation between model and code coverage possible?
Is code coverage for a model equal to code coverage of generated code?
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Carl-Jakob Ulmer
2015 年 9 月 16 日
コメント済み: Sebastian Castro
2015 年 9 月 18 日
Hi,
I use Simulink Verification and Validation toolbox to measure the code coverage while simulating the model with an automated test execution. In coverage settings I checked "Decision" and "Condition" and get in the coverage report a C1 and D1 result.
My question is how this results correlate with the code coverage of the generated code? Is it same? E.g. C1 and D1 is 100%, do I automatically have 100% for the generated code?
Thanks
Simulink version: R2014a
2 件のコメント
Sebastian Castro
2015 年 9 月 18 日
Yes, the same principles hold for Stateflow... so you should really test code coverage as well if you can!
採用された回答
Sebastian Castro
2015 年 9 月 16 日
編集済み: Sebastian Castro
2015 年 9 月 16 日
Not necessarily... Although having 100% model coverage makes it much more likely to have 100% code coverage.
There are some factors that may cause a disparity between model and code coverage, such as optimizations in the generated code, unsupported blocks in Simulink V&V that generate more logical expressions/if-else statements in the code, legacy hand-code that may be in your model (and not analyzed by Simulink V&V), and so on.
On that note, starting with either R2015a, you can collect coverage from external C hand-code that may be in your model in the form of S-Functions.
We usually recommend using a code coverage tool to complement model coverage. Embedded Coder lets you interface with a few third-party tools so you can do this in Software-in-the-loop (SIL) or Processor-in-the-loop (PIL) modes directly from Simulink.
- Sebastian
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その他の回答 (1 件)
Jeevan Thomas
2015 年 9 月 17 日
Coverage of a model doesn't necessarily reflect coverage of generated code.
In the generated code, there will be utility functions/routines generated as part of block settings (for ex: rounding, saturate on integer overflow, div-by-zero etc) which will not be covered using Simulink V&V.
Also optimization settings plays a part too.
For code coverage, you could try tools such as BTC EmbeddedTester (works better with TargetLink as code generator), ReactisForC, BullEyeCoverage etc.
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