output data type of a simple discrete TF and its VHDL code generation

Hi, i want to design simple filter using discrete TF block TF=(1/(1+ 0.1z^-1 + 0.1z^-2)) and writing its VHDL code to be synthesized in cadence. i checked with input of const block=2 with default data type inherited and ufixdt(1,16), it works well.

but i dont know when it is synthsized in cadence will it provide me input port where 4bit ADC can be connected (ADC is driveing block). my target input to the discrete filter block which accepts 4bit signal from ADC. how can a 4bit filter be designed. does the input constant block data type in simulink affects the synthesized code. e.g in simulink run, scope give same result either inherited ... or ufixdt(1,16) ? thanks

[Stephen23]

Here is the original question, just in case Safiya decides to delete the text of their question as they have with some other questions:

Hi, i want to design simple filter using discrete TF block TF=(1/(1+ 0.1z^-1 + 0.1z^-2)) and writing its VHDL code to be synthesized in cadence. i checked with input of const block=2 with default data type inherited and ufixdt(1,16), it works well.

but i dont know when it is synthsized in cadence will it provide me input port where 4bit ADC can be connected (ADC is driveing block). my target input to the discrete filter block which accepts 4bit signal from ADC. how can a 4bit filter be designed. does the input constant block data type in simulink affects the synthesized code. e.g in simulink run, scope give same result either inherited ... or ufixdt(1,16) ? thanks

Answer 1

[Tim McBrayer]

HDL Coder will generate code based off your Simulink model. If you provide a 16-bit input (either implicitly or explicitly defined) via your Constant block, the Transfer Function implementation will have a 16 bit data path. If you need a 4 bit data path, I would suggest changing your input to provide a 4-bit data path.

Whether the input is signed or unsigned is also important; in your case this depends entirely upon the data type of the 4-bit ADC on your board. Since you have specific hardware you are targeting I would modify your model so that your target subsystem is accepting data that is identical to the hardware that you need to interface with.

[Safiya]

Thankyou! for your reply, Initially Input signal varies from 0 to 1.5V and then stables after 60usec to 20mV. steady state level is 20mV. actually this comes from ADC to be fed to Type-III compensator. thank you