FPGA Data Capture in Custom Board

I have a custom cyclone v soc board. I'm trying to follow along with debug IP core using FPGA Data Capture. https://www.mathworks.com/help/hdlcoder/ug/debug-ip-core-using-fpga-data-capture.html . The FPGA Data Capture interface does not appear for me as shown in step 1.2 of HDL Workflow Advisor. How do I add this interface to my custom reference design. Will HDL Workflow Advisor automatically add the appropriate IP core to the qsys project based on what signals I want to log?

I think part of the problem is I don't have any FDC block in my library:

As you can see I do have the HDL Verifier Support Package for Intel Boards installed but there is no FPGA Data Capture block. I can not find it when searching for it either. Does this block exist in some other package or is there something wrong with my install?

Answer 1

[Naresh Challa]

Hi John,

The FPGA Data Capture feature is enabled by default for most reference designs. The primary requirement is that HDL Verifier must be installed.

If you have already installed HDL Verifier, please check the reference design parameter:

EnableJTAGFPGADataCapture

Ensure this parameter is set to true, as this controls the visibility of the option in Step 1.2.

We don't have any library blocks for FPGA Data Capture in SIMULINK library.

Thanks,

Naresh Challa

Answer 2

[John]

Is that a variable that should be declared within the plugin_rd() function? My HDL coder reference design uses a custom Qsys design that I delcared in the plugin_rd function:

hRD.addCustomQsysDesign( ...
    'CustomQsysPrjFile', 'system_soc.qsys');

Is there some IP core that needs to be included in the Qsys project as well? I tried checking the variable you mentioned and it is currently undefined:

>> EnableJTAGFPGADataCapture
Unrecognized function or variable 'EnableJTAGFPGADataCapture'.

You say there are no library blocks for FPGA Data Capture but then why does does HDL verifier ask for an Active FDC block:

There has to be some block that acts at the data sink to receive the captured signals.

Answer 3

[Naresh Challa]

Hi John,

EnableJTAGFPGADataCapture, is a referece design parameter you can check as below

hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Altera QUARTUS II');
hRD.EnableJTAGFPGADataCapture;

In the second workflow (using the Simulink Toolstrip), you need to manually integrate the FPGA Data Capture component into your Quartus project. Please follow these steps:

• GENERATE: in this step Use the Generate FDC Component option to create the FPGA Data Capture hardware component based on your requirements.

This step will:

a) Add the FPGA Data Reader block to your current Simulink model.

b) Generate the RTL code for FPGA Data Capture, which you need to integrate into your Quartus design.

• ACTIVE DATA CAPTURE BLOCK : select the intigrated FPGA Data reader as aactive block, and pin it.
• Integrate the generated RTL code into your Quartus project.(Out side SIMULINK perform manually )
• Generate the FPGA bitstream outside Simulink using Quartus.
• PREPARE : use this step, to load the generated bitstream onto the FPGA using the Simulink Toolstrip. and capture the data.

also refer this section in documentation page : Open the FPGA Data Capture Component Generator

Thanks,

Naresh Challa

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