When generating HDL code with HDL Coder for a 2-D Look Up Table block, I observed different behavior between VHDL and Verilog for the same lookup table access:
- In VHDL, the generated code uses
to_integer(add_cast + resize(mul_temp, 32))
which ensures that everything is resized into a 32-bit signed domain, producing a deterministic index.
- In Verilog, however, the generated code was:
$signed({1'b0, prelookup_idx}) + alpha2_D_Lookup_Table_mul_temp_2
Here, prelookup_idx is only 2 bits, while mul_temp_2 is 35 bits signed. The result is a 35-bit signed expression, and if any bit in the operands propagates X, the whole lookup table output becomes X in Vivado simulator.
Solution
To mimic the VHDL resize behavior, the Verilog code needs explicit truncation and casting:
wire signed [31:0] add_cast_2 = $signed({{30{1'b0}}, prelookup_idx});
wire signed [31:0] mul_temp_2_resized = alpha2_D_Lookup_Table_mul_temp_2[31:0];
wire signed [31:0] idx2 = add_cast_2 + mul_temp_2_resized;
assign alpha2_D_Lookup_Table_tableout3 = alpha2_D_Lookup_Table_7[idx2[5:0]];
With this change:
- The 35-bit value is truncated to 32 bits (matching the VHDL resize).
- The addition is performed in a 32-bit signed domain.
- The X propagation issue in Verilog simulation disappears.
Conclusion
There is a subtle difference between HDL Coder’s VHDL and Verilog backends regarding resize handling.
- VHDL always produces a deterministic integer with resize + to_integer.
- Verilog can leave the expression at a wider signed width, which increases the chance of X propagation.
Explicit truncation/casting in Verilog aligns its behavior with VHDL and resolves the simulation mismatch.
HDL Coder version is 25.1.
