I want to generate code combining Platform Architecture(MCU Peripherals), Functional Architecture, Logical Architecture with Schedular so how i can connect all components.
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I want to understand how i can generare RTE layer(schedular) in system composer.
i want to use Platform Architecture for MCU Drivers code in S-function. which will be connected to schedular component (Statechart). And schedular will be connected to Functional Architecture and Functional Architecture will be linked to Logical Architecture and with theirs simulink behavior models.
can i generate deployable code by system composer by following avobe workflow?
how i should connect schedular(Port interface for function call) to functional Archicteure and how i can send response of task complition to Schedular component?
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