Changing system Frequency "non-integer value" for OFDM example HDL coder

Hello,

I am trying to generate OFDM IP (VHDL) using HDL coder for a fractional system clock like 62.579MHz (Fsystem) and a sampling frequency of 1.95559375MHz [Fs] (32xFsystem).

Please note due to hardware restriction, I am oblige to use fractional system clock. This is one solution I am trying, my base clock is 51.2MHz.

My IP was working on different system with 62.5MHz clock that is multiple of 125MHz unlike 51.2MHz clock.

In this case: The HDL coder is unable to generate a VHDL code, I get the attached error.

"IP core genratio workflow targeting VHDl language is not supported"

Is this error known?

Thanks in advance for your help.

-BR./

Vaibhav

[Vaibhav BHATNAGAR]

There is an observation:

For previous configuration, I was using to generate an AXI4 based IP for MpSoC (Xilinx Ultrascale+) where VHDL generation was easy.

Now I am trying to generate a VHDL IP for Spartan-6 lx series, and I found that for the same Frequency configuratio for example : 51.2Mhz Fsystem clock, and 1.6 Fs for MPSoC it vhdl generation pass easily, however with ISE tool and spartan-6 it stops at the VHDL generation with the same error that I repored in my earlier post.

Is the VHDL generation not possible for Spartan-6 for an OFDM IP?

Thanks a lot for comments.

-BR./

Vaibhav

[Walter Roberson]

The error report is not about frequency problems (those might be a problem later.) The error report is about VHDL not being supported when there is a Model Reference HDL architecture.

[Vaibhav BHATNAGAR]

Thanks for your comment.

Agree with you.

That is why I am wandering why only for Spartan-6 the IP generation the model is not valid.

The error is not very clear?

Answer 1

[Satwik]

Hello @Vaibhav BHATNAGAR,

I believe the error is due to a known limitation for Custom IP Core Generation, mentioned in the following MathWorks documentation:

https://www.mathworks.com/help/hdlcoder/alterasochdlcoder/ug/generate-a-custom-ip-core-for-altera-soc-platform-from-simulink.html#buh1915-3

It states that if your target language is VHDL, the DUT cannot contain a model reference.

I hope this helps!