Unable to See the Constant Sine Wave Data in NI FPGA After Some Time Duration.

Hello,

I have created a sine wave FPGA bitfile using a Simulink block. In this model, I replaced the Clock block with a Counter block, as the Clock block was not suitable for VHDL generation. However, I am experiencing issues with the waveform not appearing correctly after some time.

Can I Know The Reson and Also, Is there any Other Way to Use Clock.

I have attached the waveform observations from the NI PXIe-7868R for the sine wave model at the initial time, after 15 minutes, and after 30 minutes.

Thank you.

Initial Condition :

After 15 mins :

After 30 min :

Answer 1

[Abhishek Kumar Singh]

Hi @Madhusudan,

Regarding the waveform observations, it appears that the frequency seems lower in the second image due to the expanded x-axis. This visual scaling can affect the perception of frequency changes, so it's important to verify the actual frequency using measurement tools. Conclusions based solely on visual inspection might not be reproducible, consistent, or easy to troubleshoot.

It could be the case that the Counter block you used to replace the Clock block might not be configured correctly for your desired frequency. Please ensure that the counter's increment rate and overflow settings align with the timing requirements of your sine wave generation.

Over time, the clock source driving the Counter block might experience drift or jitter, leading to waveform inaccuracies. This could result from temperature variations or power supply fluctuations affecting the clock source.

If possible, consider using an external stable clock source to drive your design, which can help ensure minimal drift over time.

[Madhusudan]

hello @Abhishek Kumar Singh

i am ataching the Simulink file So can you go throgh this once you will understand

Sampling time is 0.2e-6

thank you