Issues with SIL Implementation and CCS Integration for AM263P4 using MATLAB Simulink and Embedded Coder

I'm using an AM263P4 control card with MATLAB Simulink (R2024b Update 3) and the Embedded Coder Hardware Support Package for TI AM26x Processors (v24.2.0.12). I can successfully build and deploy to hardware, but unable to import the generated C code into Code Composer Studio (CCS). And the debug option is disabled, and I can't run or debug for manually added generated code folder to workspace.

To bypass this, I attempted Software-in-the-Loop (SIL) implementation. The build succeeded after updating the build configuration to specify and including GPIO driver paths in Custom Code -> Include Directories. However, during simulation, I encounter undefined reference errors for GPIO functions (e.g., GPIO_setDirMode), suggesting missing or unlinked drivers required for simulation. I tried manually linking libraries, but the issue persists.

Error message:

build summary:

0 of 1 models built (1 models already up to date) Build duration: 0h 0m 3.6275s

Simulation

### Preparing to start SIL simulation ... ### Using toolchain: MinGW64 | gmake (64-bit Windows) ### Creating 'E:\Qsync\TestfrCCS1_ert_rtw\sil\TestfrCCS1.mk' ... ### Building 'TestfrCCS1': "$(MINGW_ROOT)\mingw32-make.exe" -j 6 -l 6 -Oline -f TestfrCCS1.mk all

(..............few more lines and then.......)

"### Creating standalone executable "./TestfrCCS1.exe" ..." "C:\PROGRA~3\MATLAB\SUPPOR~1\R2024b\3P778C~1.INS\MINGW_~1.INS\bin/g++" -static -m64 -o ./TestfrCCS1.exe @TestfrCCS1.rsp -Wl,--start-group @TestfrCCS1_ref.rsp E:/Qsync/TestfrCCS1_ert_rtw/coderassumptions/pwslib/TestfrCCS1_ca.lib -Wl,--end-group -lws2_32 hostobj/MW_GPIOOUT.obj:MW_GPIOOUT.c:(.text+0x243): undefined reference to `GPIO_setDirMode' hostobj/MW_GPIOOUT.obj:MW_GPIOOUT.c:(.text+0x261): undefined reference to `GPIO_setTrigType' hostobj/MW_GPIOOUT.obj:MW_GPIOOUT.c:(.text+0x286): undefined reference to `GPIO_bankIntrEnable' hostobj/MW_GPIOOUT.obj:MW_GPIOOUT.c:(.text+0x320): undefined reference to `GPIO_bankIntrDisable' hostobj/MW_GPIOOUT.obj:MW_GPIOOUT.c:(.text+0x33a): undefined reference to `GPIO_setTrigType' collect2.exe: error: ld returned 1 exit status mingw32-make: *** [TestfrCCS1.mk:305: TestfrCCS1.exe] Error 1 E:\Qsync\TestfrCCS1_ert_rtw\sil>echo The make command returned an error of 2 The make command returned an error of 2 E:\Qsync\TestfrCCS1_ert_rtw\sil>exit /B 1

An error occurred while calling the SIL or PIL target connectivity implementation.

Caused by:

• Error(s) encountered while building "TestfrCCS1"

Answer 1

[Akshat Dalal]

Hi Ramakrishna,

I had faced the same issue some time back. The issue turned out to be that I had named one of the source files same as the model. This confused the SIL code-generation process. I would recommend you to once recheck if this is the case for you also. Also, could you please verify the includes and the function names being called from the model? Incorrect naming may also cause this issue.

Thanks

[Ramakrishna]

Hi Akshat,

Thank you for your suggestion. I had encountered the issue you mentioned regarding naming conflicts with the model, but I was able to resolve it by adding the appropriate .h files. I appreciate your advice—it was helpful to cross-check this aspect during debugging.

However, I am now encountering a different issue during the SIL simulation process. The simulation stops with the following error:

"### Creating standalone executable "./TestfrCCS1.exe" ..." "C:\PROGRA~3\MATLAB\SUPPOR~1\R2024b\3P778C~1.INS\MINGW_~1.INS\bin/g++" -static -m64 -g -o ./TestfrCCS1.exe @TestfrCCS1.rsp -Wl,--start-group @TestfrCCS1_ref.rsp E:/TestfrCCS1_ert_rtw/coderassumptions/pwslib/TestfrCCS1_ca.lib -Wl,--end-group -lws2_32 "### Created: ./TestfrCCS1.exe" "### Successfully generated all binary outputs." E:\TestfrCCS1_ert_rtw\sil>exit /B 0 ### Starting SIL simulation for component: TestfrCCS1 ### Application stopped ### Stopping SIL simulation for component: TestfrCCS1

Target application caught the signal "SIGSEGV" at time 0 and has stopped. Captured stderr messages are displayed above. Consider using SIL debugging to investigate the problem.

The build process seems to complete successfully, but the target application fails with a segmentation fault (SIGSEGV) during the SIL simulation. I am currently investigating this and considering enabling SIL debugging to trace the root cause. If you have encountered this type of issue or have any recommendations for debugging such errors, I would greatly appreciate your insights.

Thanks again for your help!

Best regards,

Ramakrishna