Assignment of elements of vector inside for-loop with conditional logics

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John
John 2024 年 11 月 19 日 21:50
コメント済み: John 2024 年 12 月 1 日 12:35
Hi there,
I need to implement in Simulink the following logic illustrated as a simplified pseudo code below. The idea is need to update a vector based on condition inside a for-loop. Some condition may be not perform any operation on the vector elements at all.
Vector = [0, 0, 0];
For iteration=1:3
If iteration<=1
Vector(1) = 1;
elseif iteration<=2
Vector(2) = 3;
else
end
end
I am trying to avoid a memory block to use the whole vector from previous iteration to current iteration because of the computation effort needed to copy the whole vector. The way assignment block works within a for-loop serves this purpose well as desribed here https://www.mathworks.com/help/simulink/slref/iterated-assignment-with-assignment-block.html. However, because of the conditional logic, I am not sure if it is possible.
Appreciate for any suggestions on the implementation

回答 (1 件)

Umar
Umar 2024 年 11 月 20 日 9:19

Hi @John,

You have a specific condition-based logic that needs to update elements of a vector (Vector = [0, 0, 0]) during each iteration of a loop. The conditions dictate that only certain elements of the vector should be updated based on the current iteration index. The goal is to avoid copying the entire vector for every iteration, which can be computationally expensive. Here are the implementation steps listed below.

1. Set Up the Model: - Open Simulink and create a new model. - Add a For Iterator Subsystem from the Simulink library.

2. Initialize the Vector: - Within the For Iterator Subsystem, initialize your vector using a Constant block or an Inport block with values [0, 0, 0]. This will serve as your initial vector state.

3. Add an Assignment Block: - Drag an Assignment block into your For Iterator Subsystem. This block will allow you to update specific elements of the vector based on the iteration index. - Configure this block to accept two inputs: one for the vector and another for the new value to be assigned.

4. Configure Loop Logic: - Use a Switch block or Multiport Switch block to implement your conditional logic: - Connect the output of the For Iterator to control which element of the vector is updated based on the current iteration. - For iteration <= 1, connect it to update Vector(1). - For iteration <= 2,connect it to update Vector(2). - If none of these conditions are met (i.e., for iteration > 2), simply pass through the current value of that element without making any updates.

5. Connect Outputs: - Ensure that after each update, you connect the output of your Assignment block back into itself or use it as an input for subsequent iterations, allowing it to carry forward any changes made during previous iterations.

6. Final Output: - After exiting the For Iterator loop, connect an Outport block to capture the final state of your vector.

Example Configuration

- In your Assignment block, you might set it up as follows: - Inputs: - First input: Current state of `Vector` - Second input: New value based on conditions - Assignments in your logic:

      if iteration == 1
        Vector(1) = 1;
      elseif iteration == 2
        Vector(2) = 3;
      end

By using this approach, you minimize memory usage since only specific elements are updated rather than copying and reassigning the whole vector.

Hope this helps.

  7 件のコメント
Walter Roberson
Walter Roberson 2024 年 12 月 1 日 5:00
Assignment Block in Conditional Subsystem
If you place an Assignment block in a conditional subsystem block, a hidden signal buffer (which is equivalent to a Signal Copy block) is inserted in many cases, and merging of signals from Assignment blocks with partial writes can cause an error.
However, if you select the Ensure outport is virtual parameter for the conditional subsystem Outport block, such cases are supported and partial writes to arrays using Assignment blocks are possible. See Ensure Output Port Is Virtual.
The link describes ensuring the output port is virtual, which bypasses the Signal Copy block, as you requested. Unfortunately to me the documentation is not clear as to what it means to have a virtual output port. The examples show that it does have an effect on output, but at the moment I do not understand what the difference in output is.
John
John 2024 年 12 月 1 日 12:35
My understanding on the virtual outport is limited but I am putting below so that you are welcome to point out my mistakes if having
  1. In specific cases, such as in the example at https://www.mathworks.com/help/simulink/ug/ensure-outport-is-virtual.html, we could see virtual and non-virtual result in different values coming out of the logics
  2. There are many other cases, or I might say most of the cases, the results are not different
  3. The default setup is always non-virtual and in many cases, we probably often ignore the fact that it is non-virtual without further analysis. I think because of 2, it is acceptable
  4. There are some specific logics that Simulink doesn't allow non-virtual, and we have to set it as virtual. For example, I use Simulink examle openExample('simulink/PartialWriteSignalsWithMergeBlockExample') and then modify the outport from virtual to non-virtual and it caused the following error: "The signal from 'ex_partial_write_single_merge/Run_Process_SubSystem/Assignment' output port 1 is required to be persistent, hence this signal cannot be connected to a Merge block".
I am looking forward to further discussions on this topic.

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