Shift Operations in Universal Shift Register Return Zero in HDL Verifier and Vivado, While Parallel Load Works Correctly

I've designed a universal shift register and tried to test it using HDL Verifier and the Vivado simulator. When I input a sample number, like 1024, and attempt a left shift operation, I set the select line to "10" (configured using a bus creator). The other two inputs are appropriately set with values in place of the LSB or MSB after each operation. However, instead of the expected shifted output, I only get a zero at the output. The same issue occurs for the right shift operation, where it also outputs zero. The only function that works correctly is parallel loading, which suggests that the select line is configured properly.

Interestingly, when I tested this module with a hand-written testbench in Vivado, it worked perfectly as intended. In my setup, constants are of boolean type, except for the parallel-in input, which is uint32. I’ll attach the co-simulation block parameters and the Verilog testbench for reference. Any insights or suggestions on what might be causing this issue would be greatly appreciated!