Can't understand individual VHDL files generated.

I have generated hdl code from a simulink model, but it has created many files. I don't have any prior experience with VHDL and can't understand what is each file doing. Is there any way to know what the individual VHDL files are doing?

Answer 1

[Aditya]

Hi Jaykishan,

Please refer to this MATLAB documentation to understand the generated HDL code:

https://in.mathworks.com/help/hdlcoder/gs/example-generating-hdl-code-from-a-simulink-model.html#:~:text=Code%20Generation%20Complete.-,View%20HDL%20Code%20Generation%20Files,-A%20folder%20icon

This documentation explains the file structure and how you can understand different parts, as well as the mapping between Simulink components and the generated code.