How can I generate IP core for xilinx spartan 6 fpga in matlab

I am getting errors oin ipcore generation workflow : Main error is i am unable to generate AXI-4 LITE interfaces for inputs

Answer 1

[naren]

The only workflow that worked for me was FPGA Turnkey.

Basically I took an led counter model and used the HDL Workflow advisor in FPGA Turnkey mode to implement it on my spartan 6 (xc6slx9) hardware .