Matlab Buildroot: How do I create an AXI-Stream supporting DeviceTree for a Zynq CustomBoard (PynqZ2)?

I am currently trying to get the AXI-Stream example for the PynqZ2 (a Zynq based board) to work.

I've followed the therefore necessary steps according to the Simulink SFIR Stream Example.

However, I couldn't get it to work.

What I've already got to work:

I've created a customLinuxImage using the MatlabBuildroot Tool. After I successfully deployed it to the Board, I was able to get the LED_Blinking Example to work. The therefore needed DeviceTree came was copied from the ZedBoard and the UART Output Port was Changed from 1 to 0.

I Then tried deploying the AXI-Stream application to the same LinuxImage and got a connectionTimedOut Error. I Tried to deploy it manually but then noticed, that apparently the "mwipcore0:mm2s" and "mwipcore0:s2mm" where missing. Even iio_info didn't list them.

Thats why I am sure, the DeviceTree did not list the AXI-Stream Interfaces as they where not configured.

When i tried to configure them by adding zynq-mw-axistream-common.dtsi to deviceTreeSources to include.

In there i found the following code:

#include "zynq-mw-cma.dtsi"
#include "xilinx-mw-axistream-dma.dtsi"

&axi4stream_mm2s {
	reg = <0x40020000 0x10000>;
	dma-channel@0  {
		interrupts = <0x0 0x1d 0x4>;
	};
};
&axi4stream_s2mm {
	reg = <0x40030000 0x10000>;
	dma-channel@0  {
		interrupts = <0x0 0x1e 0x4>;
	};
};

&mwipcore0 {
	dmas = <&axi4stream_mm2s 0 
                &axi4stream_s2mm 0>;
	dma-names = "mm2s", "s2mm";
};

Shouldn't this add afformentioned hardware interfaces, so that they should be discovered? Do I need to configure them further? If so, how do I accomplish that?

Also, the DeviceTree for the pynqz2 I am using was copied from their official GitRepository, it contains at least one error.

/*
 * TUL Pynq-Z2 board DTS
 */
/dts-v1/;
#include "zynq-7000.dtsi"

/ {
	model = "Zynq PYNQ-Z2 Development Board";
	compatible = "digilent,zynq-artyz", "xlnx,zynq-7000";

	aliases {
		ethernet0 = &gem0;
		serial0 = &uart0;
		spi0 = &qspi;
		mmc0 = &sdhci0;
	};

	memory {
		device_type = "memory";
        reg = <0x0 0x20000000>;
        
		/*
         *   reg = <0x0 0x10000000>;
         *   Original;
         *   wrong size, as the RAM is 512MB, not 265MB
         */
	};

	chosen {
		bootargs = "";
		stdout-path = "serial0:115200n8";
	};

	usb_phy0: phy0 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
		reset-gpios = <&gpio0 46 1>;
	};
};

&clkc {
	ps-clk-frequency = <50000000>;
};

&gem0 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&ethernet_phy>;

	ethernet_phy: ethernet-phy@0 { /* rtl8211e-vl */
		reg = <1>;
	};
};

&qspi {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&sdhci0 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&uart0 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usb0 {
	status = "okay";
	dr_mode = "host";
	usb-phy = <&usb_phy0>;
};

Compiling the image did actually work though. When I booted the file and used Putty to read the Serial Output for a better understanding what's going wrong I got The following output.

4531328 bytes read in 395 ms (10.9 MiB/s)
reading devicetree.dtb
15676 bytes read in 17 ms (900.4 KiB/s)
reading uramdisk.image.gz
19804823 bytes read in 1675 ms (11.3 MiB/s)
## Booting kernel from Legacy Image at 02080000 ...
   Image Name:   Linux-4.9.0-mathworksMV
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    4531264 Bytes = 4.3 MiB
   Load Address: 00008000
   Entry Point:  00008000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 04000000 ...
   Image Name:
   Image Type:   ARM Linux RAMDisk Image (uncompressed)
   Data Size:    19804759 Bytes = 18.9 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 02000000
   Booting using the fdt blob at 0x2000000
   Loading Kernel Image ... OK
   Loading Ramdisk to 0d842000, end 0eb25257 ... OK
   Loading Device Tree to 0d83b000, end 0d841d3b ... OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.9.0-mathworksMV (dev@matBuildRoot) (gcc version 6.3.1 20170109 (Linaro GCC 6.3-2017.02) ) #1 SMP PREEMPT Wed Jan 10 17:50:18 CET 2024
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt:Machine model: Zynq PYNQ-Z2 Development Board
[    0.000000] earlycon: cdns0 at MMIO 0xe0000000 (options '115200n8')
[    0.000000] bootconsole [cdns0] enabled
[    0.000000] OF: reserved mem: failed to allocate memory for node 'linux,cma'
[    0.000000] cma: Reserved 128 MiB at 0x05800000
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] percpu: Embedded 14 pages/cpu @cfd8f000 s27916 r8192 d21236 u57344
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 65024
[    0.000000] Kernel command line: earlycon root=/dev/ram rw
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Memory: 97596K/262144K available (6144K kernel code, 487K rwdata, 2368K rodata, 1024K init, 181K bss, 33476K reserved, 131072K cma-reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xd0800000 - 0xff800000   ( 752 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0700000   (7136 kB)
[    0.000000]       .init : 0xc0a00000 - 0xc0b00000   (1024 kB)
[    0.000000]       .data : 0xc0b00000 - 0xc0b79ca0   ( 488 kB)
[    0.000000]        .bss : 0xc0b79ca0 - 0xc0ba7464   ( 182 kB)
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] efuse mapped to d0800000
[    0.000000] slcr mapped to d0802000
[    0.000000] L2C: platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C: DT/platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C-310 erratum 769419 enabled
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB
[    0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x46460001
[    0.000000] zynq_clock_init: clkc starts at d0802100
[    0.000000] Zynq clock init
[    0.000012] sched_clock: 64 bits at 325MHz, resolution 3ns, wraps every 4398046511103ns
[    0.007830] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4af477f6aa, max_idle_ns: 440795207830 ns
[    0.018828] Switching to timer-based delay loop, resolution 3ns
[    0.024813] clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 551318127 ns
[    0.033799] timer #0 at d080a000, irq=17
[    0.038345] Console: colour dummy device 80x30
[    0.042613] console [tty0] enabled
[    0.045982] bootconsole [cdns0] disabled
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.9.0-mathworksMV (dev@matBuildRoot) (gcc version 6.3.1 20170109 (Linaro GCC 6.3-2017.02) ) #1 SMP PREEMPT Wed Jan 10 17:50:18 CET 2024
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt:Machine model: Zynq PYNQ-Z2 Development Board
[    0.000000] earlycon: cdns0 at MMIO 0xe0000000 (options '115200n8')
[    0.000000] bootconsole [cdns0] enabled
[    0.000000] OF: reserved mem: failed to allocate memory for node 'linux,cma'
[    0.000000] cma: Reserved 128 MiB at 0x05800000
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] percpu: Embedded 14 pages/cpu @cfd8f000 s27916 r8192 d21236 u57344
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 65024
[    0.000000] Kernel command line: earlycon root=/dev/ram rw
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Memory: 97596K/262144K available (6144K kernel code, 487K rwdata, 2368K rodata, 1024K init, 181K bss, 33476K reserved, 131072K cma-reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xd0800000 - 0xff800000   ( 752 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0700000   (7136 kB)
[    0.000000]       .init : 0xc0a00000 - 0xc0b00000   (1024 kB)
[    0.000000]       .data : 0xc0b00000 - 0xc0b79ca0   ( 488 kB)
[    0.000000]        .bss : 0xc0b79ca0 - 0xc0ba7464   ( 182 kB)
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] efuse mapped to d0800000
[    0.000000] slcr mapped to d0802000
[    0.000000] L2C: platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C: DT/platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C-310 erratum 769419 enabled
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB
[    0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x46460001
[    0.000000] zynq_clock_init: clkc starts at d0802100
[    0.000000] Zynq clock init
[    0.000012] sched_clock: 64 bits at 325MHz, resolution 3ns, wraps every 4398046511103ns
[    0.007830] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4af477f6aa, max_idle_ns: 440795207830 ns
[    0.018828] Switching to timer-based delay loop, resolution 3ns
[    0.024813] clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 551318127 ns
[    0.033799] timer #0 at d080a000, irq=17
[    0.038345] Console: colour dummy device 80x30
[    0.042613] console [tty0] enabled
[    0.045982] bootconsole [cdns0] disabled
[    0.049925] Calibrating delay loop (skipped), value calculated using timer frequency.. 650.00 BogoMIPS (lpj=3250000)
[    0.050004] pid_max: default: 32768 minimum: 301
[    0.050221] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.050274] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.051205] CPU: Testing write buffer coherency: ok
[    0.051278] ftrace: allocating 23474 entries in 69 pages
[    0.105022] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.105140] Setting up static identity map for 0x100000 - 0x100058
[    0.268277] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.268407] Brought up 2 CPUs
[    0.268458] SMP: Total of 2 processors activated (1300.00 BogoMIPS).
[    0.268486] CPU: All CPU(s) started in SVC mode.
[    0.269500] devtmpfs: initialized
[    0.275513] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[    0.276009] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.283875] pinctrl core: initialized pinctrl subsystem
[    0.285347] NET: Registered protocol family 16
[    0.287708] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.318368] cpuidle: using governor ladder
[    0.330008] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[    0.330054] hw-breakpoint: maximum watchpoint size is 4 bytes.
[    0.330243] zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xd0840000
[    0.330797] zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
[    0.367257] SCSI subsystem initialized
[    0.369738] usbcore: registered new interface driver usbfs
[    0.369911] usbcore: registered new interface driver hub
[    0.370095] usbcore: registered new device driver usb
[    0.370920] media: Linux media interface: v0.10
[    0.371125] Linux video capture interface: v2.00
[    0.371270] pps_core: LinuxPPS API ver. 1 registered
[    0.371330] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[e-mail]>
[    0.371461] PTP clock support registered
[    0.371588] EDAC MC: Ver: 3.0.0
[    0.373024] Advanced Linux Sound Architecture Driver Initialized.
[    0.378591] clocksource: Switched to clocksource arm_global_timer
[    0.464864] NET: Registered protocol family 2
[    0.465812] TCP established hash table entries: 2048 (order: 1, 8192 bytes)
[    0.465909] TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
[    0.466006] TCP: Hash tables configured (established 2048 bind 2048)
[    0.466116] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    0.466199] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    0.466473] NET: Registered protocol family 1
[    0.466859] Trying to unpack rootfs image as initramfs...
[    2.366422] Freeing initrd memory: 19344K (cd842000 - ceb26000)
[    2.366854] hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
[    2.368710] futex hash table entries: 512 (order: 3, 32768 bytes)
[    2.370020] workingset: timestamp_bits=30 max_order=16 bucket_order=0
[    2.371490] io scheduler noop registered
[    2.371553] io scheduler deadline registered
[    2.371649] io scheduler cfq registered (default)
[    2.375731] dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
[    2.375808] dma-pl330 f8003000.dmac:         DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
[    2.377111] e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 25, base_baud = 6250000) is a xuartps
[    3.007346] console [ttyPS0] enabled
[    3.011887] xdevcfg f8007000.devcfg: ioremap 0xf8007000 to d081c000
[    3.019208] [drm] Initialized
[    3.040223] brd: module loaded
[    3.053668] loop: module loaded
[    3.060248] zynq-qspi e000d000.spi: couldn't determine configuration info
[    3.067013] zynq-qspi e000d000.spi: about dual memories. defaulting to single memory
[    3.076230] libphy: Fixed MDIO Bus: probed
[    3.081969] CAN device driver interface
[    3.087594] libphy: MACB_mii_bus: probed
[    3.258751] macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 27 (00:0a:35:00:01:22)
[    3.268621] Generic PHY e000b000.etherne:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=e000b000.etherne:01, irq=-1)
[    3.280882] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    3.287531] usbcore: registered new interface driver usb-storage
[    3.293749] usbcore: registered new interface driver usbserial
[    3.299661] usbcore: registered new interface driver usbserial_generic
[    3.306227] usbserial: USB Serial support registered for generic
[    3.312299] usbcore: registered new interface driver ftdi_sio
[    3.318079] usbserial: USB Serial support registered for FTDI USB Serial Device
[    3.325745] e0002000.usb supply vbus not found, using dummy regulator
[    3.332579] ULPI transceiver vendor/product ID 0x0451/0x1507
[    3.338211] Found TI TUSB1210 ULPI transceiver.
[    3.342771] ULPI integrity check: passed.
[    3.346765] ci_hdrc ci_hdrc.0: EHCI Host Controller
[    3.351658] ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
[    3.388667] ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
[    3.395295] hub 1-0:1.0: USB hub found
[    3.399104] hub 1-0:1.0: 1 port detected
[    3.405397] mousedev: PS/2 mouse device common for all mice
[    3.411353] i2c /dev entries driver
[    3.416789] cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer at d08f6000 with timeout 10s
[    3.425482] Xilinx Zynq CpuIdle Driver started
[    3.430603] sdhci: Secure Digital Host Controller Interface driver
[    3.436754] sdhci: Copyright(c) Pierre Ossman
[    3.441129] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.498673] mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using DMA
[    3.513884] ledtrig-cpu: registered to indicate activity on CPUs
[    3.520143] hidraw: raw HID events driver (C) Jiri Kosina
[    3.543997] usbcore: registered new interface driver usbhid
[    3.549609] usbhid: USB HID core driver
[    3.563629] NET: Registered protocol family 10
[    3.569670] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.576685] NET: Registered protocol family 17
[    3.578119] mmc0: new high speed SDHC card at address 0007
[    3.586704] can: controller area network core (rev 20120528 abi 9)
[    3.590084] mmcblk0: mmc0:0007 SL16G 14.5 GiB
[    3.591925]  mmcblk0: p1
[    3.599949] NET: Registered protocol family 29
[    3.604359] can: raw protocol (rev 20120528)
[    3.608658] can: broadcast manager protocol (rev 20161123 t)
[    3.614296] can: netlink gateway (rev 20130117) max_hops=1
[    3.620063] Registering SWP/SWPB emulation handler
[    3.633044] hctosys: unable to open rtc device (rtc0)
[    3.638447] ALSA device list:
[    3.641426]   No soundcards found.
[    3.648547] Freeing unused kernel memory: 1024K (c0a00000 - c0b00000)
[    3.690890] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
Starting logging: OK
Starting mdev...
[    4.702223] xilinx-vdma 40400000.axidma: Xilinx AXI VDMA Engine Driver Probed!!
[    4.710066] Unhandled fault: imprecise external abort (0x406) at 0xbf000000
[    4.717010] pgd = c52a8000
[    4.719675] [bf000000] *pgd=057db811, *pte=050a145f, *ppte=050a145e
[    4.725926] Internal error: : 406 [#1] PREEMPT SMP ARM
[    4.731051] Modules linked in: xilinx_dma(+)
[    4.735299] CPU: 1 PID: 789 Comm: modprobe Not tainted 4.9.0-mathworksMV #1
[    4.742251] Hardware name: Xilinx Zynq Platform
[    4.746761] task: cfa437c0 task.stack: c52d2000
[    4.751307] PC is at xilinx_dma_reset+0x34/0x138 [xilinx_dma]
[    4.757030] LR is at xilinx_dma_chan_reset+0x1c/0x64 [xilinx_dma]
[    4.763095] pc : [<bf0003a0>]    lr : [<bf00186c>]    psr: 60070013
[    4.763095] sp : c52d3c00  ip : c52d3c28  fp : c52d3c24
[    4.774589] r10: 00000000  r9 : 00000000  r8 : cfdb5108
[    4.779773] r7 : cf83a310  r6 : dec0de1c  r5 : cfdb4dec  r4 : cf83a310
[    4.786286] r3 : d0940030  r2 : 00000030  r1 : c5324220  r0 : cf83a310
[    4.792797] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
[    4.799915] Control: 18c5387d  Table: 052a804a  DAC: 00000051
[    4.805640] Process modprobe (pid: 789, stack limit = 0xc52d2210)
[    4.811717] Stack: (0xc52d3c00 to 0xc52d4000)
[    4.816060] 3c00: cf83a310 0000002e cf83a310 cfdb4dec 00000000 cf83a310 c52d3c44 c52d3c28
[    4.824257] 3c20: bf00186c bf000378 c5324210 cfdb4dec 00000000 cf83a310 c52d3cb4 c52d3c48
[    4.832433] 3c40: bf002098 bf00185c 00000080 bf004127 cf83a310 c50a0a50 00000020 00000000
[    4.840608] 3c60: c5324220 00000000 cf9a6810 00000000 00000000 00000020 00000017 00000001
[    4.848786] 3c80: 00000020 00000000 c0145d88 bf001b08 cf9a6810 bf0043a0 00000000 c0b72a68
[    4.856963] 3ca0: 00000002 c2719fe4 c52d3cd4 c52d3cb8 c03faaa4 bf001b14 cf9a6810 c0b9aaf4
[    4.865139] 3cc0: bf0043a0 00000000 c52d3d04 c52d3cd8 c03f898c c03faa50 c52d3d04 c52d3ce8
[    4.873316] 3ce0: cf9a6810 cf9a6844 bf0043a0 c0b72990 00000000 00000001 c52d3d24 c52d3d08
[    4.881493] 3d00: c03f8b8c c03f86d4 00000000 bf0043a0 c03f8adc c0b72990 c52d3d4c c52d3d28
[    4.889669] 3d20: c03f69c8 c03f8ae8 cf948f5c cf9ff9b4 c06d7168 bf0043a0 c2718400 c0b400d0
[    4.897845] 3d40: c52d3d5c c52d3d50 c03f81cc c03f6944 c52d3d8c c52d3d60 c03f7ce8 c03f81b0
[    4.906022] 3d60: bf0042ab bf0044c8 c52d3d8c bf0043a0 ffffe000 00000000 bf0044c8 c2719fc0
[    4.914199] 3d80: c52d3da4 c52d3d90 c03f98bc c03f7b28 bf007000 ffffe000 c52d3db4 c52d3da8
[    4.922375] 3da0: c03fa9e4 c03f9818 c52d3dc4 c52d3db8 bf007018 c03fa9b0 c52d3e3c c52d3dc8
[    4.930552] 3dc0: c0101dbc bf00700c c52d3e14 c52d3dd8 c01e9688 a0070013 a0070013 bf004480
[    4.938728] 3de0: c506e340 cf800000 024000c0 024000c0 0000000c c01e0a8c c52d3e3c c52d3e08
[    4.946904] 3e00: c0223a44 c01b6a60 c02248d8 c01b6a60 00000008 bf004480 bf004480 c52d3f44
[    4.955082] 3e20: c506e340 bf0044c8 c2719fc0 00000001 c52d3e64 c52d3e40 c01e0ac8 c0101c8c
[    4.963258] 3e40: c52d3e64 c52d3e50 c02195a4 bf004480 c52d3f44 00000001 c52d3f1c c52d3e68
[    4.971435] 3e60: c0192a7c c01e0a68 bf00448c 00007fff bf004480 c0190348 bf000000 000b919b
[    4.979611] 3e80: 000000d7 d0911774 bf004664 d09148c0 000000d7 c0705c00 c018fc50 d090d000
[    4.987787] 3ea0: 00000000 00000000 c52d3eec c52d3eb8 c02316f0 bf003554 00000001 00000000
[    4.995962] 3ec0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[    5.004139] 3ee0: 00000000 00000000 00000000 00000000 7fffffff 00000000 000b919b 00000003
[    5.012317] 3f00: 0000017b c0108484 c52d2000 00000000 c52d3fa4 c52d3f20 c019330c c0191228
[    5.020494] 3f20: 7fffffff 00000000 00000003 c52d3f38 c0238e00 d090d000 00007910 00000000
[    5.028670] 3f40: c52d3f94 d090d000 00007910 d0914280 d09140dc d0912640 00004680 00004d90
[    5.036846] 3f60: bf0043e8 00000005 00000000 00001778 00000028 00000029 00000021 00000000
[    5.045022] 3f80: 00000018 00000000 00000000 00000000 000cd5e8 00000000 00000000 c52d3fa8
[    5.053199] 3fa0: c01082e0 c0193254 00000000 000cd5e8 00000003 000b919b 00000000 000cd6b8
[    5.061376] 3fc0: 00000000 000cd5e8 00000000 0000017b 000cd6b8 000cadd0 000cd6b8 000cc5c0
[    5.069553] 3fe0: be9645e0 be9645d0 0002691c b6f4fa42 80070030 00000003 00000000 00000000
[    5.077768] [<bf0003a0>] (xilinx_dma_reset [xilinx_dma]) from [<bf00186c>] (xilinx_dma_chan_reset+0x1c/0x64 [xilinx_dma])
[    5.088760] [<bf00186c>] (xilinx_dma_chan_reset [xilinx_dma]) from [<bf002098>] (xilinx_dma_probe+0x590/0x9e0 [xilinx_dma])
[    5.099922] [<bf002098>] (xilinx_dma_probe [xilinx_dma]) from [<c03faaa4>] (platform_drv_probe+0x60/0xac)
[    5.109505] [<c03faaa4>] (platform_drv_probe) from [<c03f898c>] (driver_probe_device+0x2c4/0x414)
[    5.118385] [<c03f898c>] (driver_probe_device) from [<c03f8b8c>] (__driver_attach+0xb0/0x114)
[    5.126916] [<c03f8b8c>] (__driver_attach) from [<c03f69c8>] (bus_for_each_dev+0x90/0xa0)
[    5.135099] [<c03f69c8>] (bus_for_each_dev) from [<c03f81cc>] (driver_attach+0x28/0x30)
[    5.143101] [<c03f81cc>] (driver_attach) from [<c03f7ce8>] (bus_add_driver+0x1cc/0x24c)
[    5.151104] [<c03f7ce8>] (bus_add_driver) from [<c03f98bc>] (driver_register+0xb0/0xf0)
[    5.159110] [<c03f98bc>] (driver_register) from [<c03fa9e4>] (__platform_driver_register+0x40/0x54)
[    5.168178] [<c03fa9e4>] (__platform_driver_register) from [<bf007018>] (xilinx_vdma_driver_init+0x18/0x24 [xilinx_dma])
[    5.179078] [<bf007018>] (xilinx_vdma_driver_init [xilinx_dma]) from [<c0101dbc>] (do_one_initcall+0x13c/0x164)
[    5.189181] [<c0101dbc>] (do_one_initcall) from [<c01e0ac8>] (do_init_module+0x6c/0x1d0)
[    5.197281] [<c01e0ac8>] (do_init_module) from [<c0192a7c>] (load_module+0x1860/0x1ec0)
[    5.205288] [<c0192a7c>] (load_module) from [<c019330c>] (SyS_finit_module+0xc4/0xd4)
[    5.213129] [<c019330c>] (SyS_finit_module) from [<c01082e0>] (ret_fast_syscall+0x0/0x1c)
[    5.221307] Code: e5933000 e0833002 e5936000 f57ff04f (e5903000)
[    5.227364] ---[ end trace c301ba603a6d8ba1 ]---
xargs: 'modprobe' terminated by signal 11
Loading drivers for discovered hardware...
[    5.276201] Registered mathworks_ip class
  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] efuse mapped to d0800000
[    0.000000] slcr mapped to d0802000
[    0.000000] L2C: platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C: DT/platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C-310 erratum 769419 enabled
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB
[    0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x46460001
[    0.000000] zynq_clock_init: clkc starts at d0802100
[    0.000000] Zynq clock init
[    0.000012] sched_clock: 64 bits at 325MHz, resolution 3ns, wraps every 4398046511103ns
[    0.007830] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4af477f6aa, max_idle_ns: 440795207830 ns
[    0.018829] Switching to timer-based delay loop, resolution 3ns
[    0.024813] clocksource: ttc_clocksource: mask: 0  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] efuse mapped to d0800000
[    0.000000] slcr mapped to d0802000
[    0.000000] L2C: platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C: DT/platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C-310 erratum 769419 enabled
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB
[    0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x46460001
[    0.000000] zynq_clock_init: clkc starts at d0802100
[    0.000000] Zynq clock init
[    0.000012] sched_clock: 64 bits at 325MHz, resolution 3ns, wraps every 4398046511103ns
[    0.007830] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4af477f6aa, max_idle_ns: 440795207830 ns
[    0.018829] Switching to timer-based delay loop, resolution 3ns
[    0.024813] clocksource: ttc_clocksource: mask: 0  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] efuse mapped to d0800000
[    0.000000] slcr mapped to d0802000
[    0.000000] L2C: platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C: DT/platform modifies aux control register: 0x02060000 -> 0x32460000
[    0.000000] L2C-310 erratum 769419 enabled
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB
[    0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x46460001
[    0.000000] zynq_clock_init: clkc starts at d0802100
[    0.000000] Zynq clock init
[    0.000012] sched_clock: 64 bits at 325MHz, resolution 3ns, wraps every 4398046511103ns
[    0.007830] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4af477f6aa, max_idle_ns: 440795207830 ns
[    0.018829] Switching to timer-based delay loop, resolution 3ns
[    0.024813] clocksource: ttc_clocksource: mask: 0  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] efuse mapped to d0[   32.861889] random: fast init done

When "discovering" the new hardware it just stops until i press a key to interrupt that process. All while never discovering anything.

I thought that just adding the standard interface libraries such as (base.dtsi or zynq-mw-axistream-iio-common.dtsi) to the DeviceTree would be enough to get the image to work but it doesn't seem to be that easy.

Any help on how to get the DeviceTree properly set so the AXi-Stream DMA interfaces show up would be greatly appreciated.

I am currently using the 2022.a Version of tools. Including, Buildroot, Simulink HDL Coder and Matlab.

Unfortunately I couldn't attach the version because MatlabBuildroot apparently does not count as a listed Mathworks product.

Best regards,

Adrian W.

Answer 1

[Adrian Wendland]

Reporting back. I finally found the error and got the axistream example working on the pynq-z2 SoC.

TLDR:

The problem was a faulty reference design. Multichannel dmas are not supported anymore. I also had to tweak the addresses of the mwipcores to match the axistream registers.

Longer version:

I tried replicating the reference design from the Axistream-Example. Notice the multichannel dma that has been used in that reference design.

As it turns out, xilinx removed the support for the multichannel dma-engine back in version 2019.1 according to their wiki.

All the example devicetrees in the buildroot repository (zybo, zed, zcu702,etc.), which use the axistream interface have two dmas listed. One for reading data from the dma and one for writing on it.

I've already contacted the mathworks support on that matter and they are working on updating their pages.

Anyway the fully created vivado-reference-design as it has been produced by the hdl-workflow advisor is shown below.

I also checked, that the configured addresses match those of the .dts files in the buildroot repository (as i copied them for my pynqz2 board).

NOTE: As far as I'm aware it's not of importance how you name your DUT in hdl-workflow-advisor. It's only important that you either assign the axilite and axistream registers accordingly, or that you later change the address-registers in the .dts files respectively.

Afterwards I exported the .xsa and .bit file. the .xsa project was used to get a general devicetree without the mwipcores yet. More information about that under this link on xilinx' wiki.

It's noteworthy that the newer versions of xilinx tools tend to use a different (probably newer) dma driver, which from my understanding doesn't work with the mwipcores.

However, we only need

• system-top.dts
• pcw.dts (defines general peripherals like ethernet, sdhc, serial,etc.)
• zynq-7000.dtsi
• ps7_init_gpl.c
• ps7_init_gpl.h
• generated .bit file

from the generated devicetree. If you take a look into pl.dtsi you can see the dma being created without the mwipcores. Since the mwipcores use the same addresses with a different driver, the file must be excluded.

Next, we need to add the mwipcores to the devicetree and for me adding the axistream_iio.dts was enough. It has to be the *_iio.dts, otherwise the dmas and mwipcore won't be listed when typing iio_info in the console on the zynq.

#include "axistream_iio.dts"

Make sure, the .dts(i) files are all in the same folder - you can source them from the zedboard directory in buildroot.

Note: If you don't use the aforementioned addresses you may need to overwrite them manually in the .dts files.

Last but not least the catalog.xml needs to be adjusted to load the .bit file and the devicetree (which is system-top.dts)

Once you build the linux-image and load it onto the pynqz2 you should be good to go. I also attached a zipped file for those who might want to use it straight away. I can't guarantee it to work on your end though.

Some last notes:

• I upgraded the xilinx-tools (vitis and vivado) from 2022.1 to 2023.2 - So I didn't test it on the 2022.1 version anymore
• I contacted the Mathworks-support and asked them to update their mathworks/buildroot setup documentation as it's fairly outdated. They complied, but I don't think it happens anytime soon.
• I got told that they try to use a yocto/petalinux layer in the near future instead of the buildroot system. You may want to check out their GIT-Repo - However, I didn't try to use it.

Best of luck working with the mathworks-buildroot,

Adrian W

[Neeraj]

Hi @Adrian Wendland,

I tried following your steps by copying the contents of 'pynqz2_axistream.zip' into the '/board/mathworks/zynq/boards/' directory and then passing the catalog file to build.py. I also provided path the Linaro 6.3.1-2017.02 toolchain. Here's what I did:

1. I used Debian 10 OS in VirtualBox for build. I did a checkout of mathworks_zynq_R23.2.0 tag.
2. The build failed at building e2fsprogs, m4, bison packages, which I managed to solve by updating the versions.
3. Finally the uboot-mathworks_zynq_R20.2.0 package complained of not being able to find zynq_pynqz2_defconfig. So I created one in the configs folder of the package by copying the contents of zynq_zed_defconfig. Since the defconfig refers to a default dts 'zynq-pynqz2', I created a flattened dts using the pynqz2 dts file you shared above and the zynq-7000.dtsi it includes using gcc, and then used dtc to generate the dtb. I copied the zynq-pynqz2.dtb into the arch/arm/dts directory of the package before the build completed. I know it's a hack, but I don't know what else to do.
4. The build completed and I copied to the sdcard.

However, while booting I only see garbled data in the uart terminal. It's not any uart setting issue since other images load fine.

Could you please provide a zip file for your sdcard image for pynqz2, so that I can boot it and see?

Did you also face the uboot pynqz2 defconfig issue in (3) above? What did you do? You used Vivado 2023.2 to generate xsa & bitfile. Which buildroot tag did you checkout?

Thanks,

Neeraj

[Neeraj]

Update:

I tried to copy Zybo's defconfig with appropriate modifications (replacing zybo with pynqz2, and uart0 instead of uart1). This time I reach until u-boot tries to load the kernel, and then it hangs at 'Starting kernel ...'.

Not sure what to do next.

Answer 2

[Adrian Wendland]

Hello Neeraj,

It's been quite a while, since I worked with that project. Attached are some files I found. They should contain devicetree structures for an axilite as well as an axistream interface. According to the Matlab Tutorial Pages (getting started with axilite I believe). I can't upload the bootable image, because Matlab doesn't allow uploads with more than 10MB...

With a working buildroot they should work out of the box. The workaround you mentioned with copying the Zybo Boards defconfig is also what I did back then. If it hangs somewhere during the boot. It may be because of an axistream interface. Did you try the image compilation with no interfaces and just a bare minimum dts?

I've also encountered some problems. An axilite image would work just fine, but using the axistream interface had me work several weeks for a fix.

Apparently Matlab uses once again outdated Software. The DTS configs of the axistream interface are not working, because the standard doesn't support these exact definitions anymore.

See https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842337/Linux+Soft+DMA+Driver for further information. A Multi-DMA connection is no longer supported since update/commit 2019.1

Last time Mathworks checked their files must have been prior to that commit...

Anyway if the devicetrees provided doesn't work, let me know and I try to upload the ramdisks somewhere else.

[Neeraj]

Thanks @Adrian Wendland, I'll give these a try. But if you can please upload the sdcard zip somewhere, google drive maybe, it'll make it worth spending time on troubleshooting. I need to be sure if I'm building buildroot correctly. Or if the interfaces are a problem. I want to have these interfaces working so that I can switch the DUT with other IPs and algorithms.

I have spent a lot of time on this to no avail. I even built a Petalinux image using ADI Linux meta-layer. The image booted, but again probing mwipcore kept failing (likely in the Linux DMA engine buffer call and it kept deferring probe until failure). As a result iio_info did not list mwipcore. Looks like buidroot is the only way as of now since it pulls in the right legacy kernel versions to support the reference design.

Looking forward to your help.

Thanks,

Neeraj

[Neeraj]

Update:

Built images using both axilite and axistream interfaces using the files you provided. Both get stuck 'Starting kernel ...'. U-boot is not able to load the kernel in both cases. So the problem is most likely in how buildroot is building and loading the images and devicetrees.

spl_load_image_fat_os: error reading image system.dtb, err - -1
reading u-boot.img
reading u-boot.img
spl_load_image_fat_os: error reading image system.dtb, err - -1
reading u-boot.img
reading u-boot.img
spl_load_image_fat: error reading image fpga.bin, err - -1
spl: error reading image fpga.bin, err - 1
reading system.dtb
spl_load_image_fat_os: error reading image system.dtb, err - -1
reading u-boot.img
reading u-boot.img


U-Boot 2017.01 (Sep 03 2024 - 08:06:48 +0530)

Model: Zynq PYNQ-Z2 Development Board
Board: Xilinx Zynq
I2C:   ready
DRAM:  ECC disabled 512 MiB
MMC:   sdhci@e0100000: 0 (SD)
reading uboot.env

** Unable to read "uboot.env" from mmc0:1 **
Using default environment

In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Model: Zynq PYNQ-Z2 Development Board
Board: Xilinx Zynq
Net:   ZYNQ GEM: e000b000, phyaddr 1, interface rgmii-id
eth0: ethernet@e000b000
Hit any key to stop autoboot:  0 
Device: sdhci@e0100000
Manufacturer ID: 3
OEM: 5344
Name: SD64G 
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 59.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
Storing default uboot environment...
Saving Environment to FAT...
writing uboot.env
FAT: Misaligned buffer address (1eb049f8)
done
reading uEnv.txt
** Unable to read file uEnv.txt **
Loading bitstream from SD/MMC/eMMC to RAM..
Device: sdhci@e0100000
Manufacturer ID: 3
OEM: 5344
Name: SD64G 
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 59.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
reading system.bit
4045682 bytes read in 524 ms (7.4 MiB/s)
  design filename = "axistream_2dma_wrapper;UserID=0XFFFFFFFF;Version=2023.2"
  part number = "7z020clg400"
  date = "2024/02/12"
  time = "19:57:33"
  bytes in bitstream = 4045564
zynq_align_dma_buffer: Align buffer at 100076 to fff80(swap 1)
Copying Linux from SD to RAM...
reading uImage
4520888 bytes read in 583 ms (7.4 MiB/s)
reading devicetree.dtb
17194 bytes read in 17 ms (987.3 KiB/s)
reading uramdisk.image.gz
19567528 bytes read in 2473 ms (7.5 MiB/s)
## Booting kernel from Legacy Image at 02080000 ...
   Image Name:   Linux-4.9.0-mathworks
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    4520824 Bytes = 4.3 MiB
   Load Address: 00008000
   Entry Point:  00008000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 04000000 ...
   Image Name:   
   Image Type:   ARM Linux RAMDisk Image (uncompressed)
   Data Size:    19567464 Bytes = 18.7 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 02000000
   Booting using the fdt blob at 0x2000000
   Loading Kernel Image ... OK
   Loading Ramdisk to 1d87a000, end 1eb23368 ... OK
   Loading Device Tree to 1d872000, end 1d879329 ... OK

Starting kernel ...

[Neeraj]

Update 2:

A blank design with no interfaces, just the zynq PS ip instance, also gets stuck the same way. Clearly, I'm not getting the buildroot build right.