QPSK transmitter and receiver HDL examples - Why there is no equalization added?

I am trying to implement a SDR on Xilinx FPGA using an example given in the Communication toolbox support package for Xilinx Zynq based radio.

https://in.mathworks.com/help/supportpkg/xilinxzynqbasedradio/ug/hw-sw-co-design-qpsk-transmit-and-receive-using-analog-devices-ad9361-ad9364.html

However this example does not contain equalization. First I though of modifying and adding an equalizer block to the system. However while searching through the internet I came across another example "HDL QPSK Transmitter and Receiver".

https://in.mathworks.com/help/hdlcoder/ug/hdlqpsktransmitterandreceiver.html

It also does not contain an equalizer.

Then I started to wonder if there is a fundamental limitation to adding an equalizer to a QPSK link.

Is there any specific reason why an equalizer is not added to the receiver in these examples?

(Eventhough I have selected the release 2022b, the examples for 2021b and 2023b also do not contain an equalizer)

Answer 1

[Ganapathi Subramanian]

Hi,

It is my understanding that you are trying to implement a SDR on Xilinx FPGA and wants to know why equalizer is not used in the example given in Communication toolbox support package for Xilinx Zynq based radio. Equalizers blocks such as linear equalizer and decision feedback equalizer doesn’t have the capability to generate HDL code. This is the reason behind not adding an equalizer to the receiver in the example.