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Bus Assignment block dimension mismatch Please help!!!

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Amardeep 2011 年 10 月 26 日
I am getting the error:
Incomming busses to block '...UpdateData/Bus Assignment' have a dimension mismatch. the signal at input port 28 of '...DataInit/Bus Assignment'is of dimensionality 1 while its corresponding signal at inport 6 of '...UpdateData/Bus Assignment' is of dimensionality 2. This error is related to a hidden SubSystem block.
I have checked the one variable which is assigned using both blocks and its dimensionality stays the same. Is it possibly the dimensions of the bus at the first inport? However there is nothing between the two bus assignments which changes the dimensions of the bus.
Please help as this is highly confusing

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Amardeep 2011 年 10 月 27 日
I have narrowed it down and its because of a change in a non-common input where I am trying to over write a [1x9] array with another [1x9] array and its insisting on the dimension change

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Amardeep 2011 年 10 月 27 日
Figured it out. My initial assignment at the top level was coming through as dimensionality (9) as I had ticked rsolve as 1D on the constant block... DOH!


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