HDL Coder Validation Model changes wiring

Hello,

my latest validation model produced by simulink hdl coder didn't work, datatype and dimension related errors were in the model. Further investigation lead me to the root cause of the error: the ports of my DUT were connected in the wrong way.

This issue might not happen very often because normally the signal inputs are all on the left site while the outputs are on the right. For keeping the model layout nice and compact I changed this convention, which lead to to error in the validation-model.

The generated model however does not have this issue.

Here are some pictures to illustrate the problem: original, generated and validation model.

Is this a bug?

Answer 1

[Nikhilesh]

As per my understanding this is the expected behaviour and I do not see any bug.

[Manuel K]

Is this mentioned anywhere? I haven't seen any reference to it in the modeling guidelines.

And if it works in one case and not in the other, I would not call this behavior expected.