how to back annotate for hdl code

Hi,

I want to convert simulink to hdl code. But the point is simulink is ideal so I am not sure this works in SPICE level or not. So, I want to back-annotate the timing information from standard cell library provided from foundary. How can I do this?

All I want to do is more practical simulation, which means including delay, in simulink level with hdl code.

Answer 1

[Tim McBrayer]

The HDL Coder Workflow Advisor can backannotate either the pre- or post- Place and Route timing information from supported synthesis tools onto the Simulink model. This takes into account not only the logic delay but also the routing delay of the FPGA.

You should use the "Generic ASIC/FPGA" target workflow, selected in step 1.1 in the HDL Workflow Advisor. Once you have selected a synthesis tool and a specific target FPGA part, examine the choices shown in step 4.3 for how to configure and use the backannotation feature.