Why discrete time integrator in HDL coder simulink library behaves completely differently with different input sampling time?

I use two constant blocks one with sampling freq of 2e-7(5 Mhz) and another with 4e-7 (2.5 Mhz) followed by two same discrete time integrators (Sample time:inherited). The first one outputs zero and the second one outputs a ramp (which is the correct result)... What am I missing here?

Why 2e-7 or 5 Mhz is not working with discrete time integrator???

[Adeel Jamal]

Model is attached for reproduction of the anomalous behavior...

[Omkar Sastry]

Hi Adeel,

Could you please attach the other artifacts required to simulate the model (like definition for Controller.InternalSignals.DataType.PLL)? Thanks!

[Adeel Jamal]

Please run the following in the matlab workspace;

Controller.InternalSignals.DataType.PLL = fixdt(1,23,4);

Answer 1

[Adeel Jamal]

In my opinion, due to the low resolution of the fractional bit length, it rounds to zero in internal calculations of discrete time integrator.

[Omkar Sastry]

Hi Adeel, yes this is exactly what is happening. The 'floor' rounding mode coupled with the type used drags the value to 0 for the K*T*u(n) calculation in the first block.