- Use generic IP core generation to generate just an IP core with multiple streaming channels, as described here: https://www.mathworks.com/help/hdlcoder/ug/map-dut-ports-to-multiple-axi-interfaces.html
- Use a reference design that is preconfigured with multiple streaming channels, as shown in this example: https://www.mathworks.com/help/hdlcoder/ug/running-audio-filter-with-multiple-axi4-stream-channels.html
Multiple outputs from HDL block in simulink
8 ビュー (過去 30 日間)
I want to take multiple outputs from one HDL block(in Simulink) simultaneously but it only has one output option port(I & Q) values as shown in the attached image.
Actually on the application side my target is zynq-706 and want to stream multiple Radio signals from FPGA(HDL block) simultaneously.But the block doesnt let me due to single output option.
Anybody having ideas or solutions are most welcome!!!!
JT Ferrara 2021 年 11 月 1 日
HDL Coder supports generating an IP core with multiple AXI4-Stream channels. There are two ways to generate such as IP core:
Note that specific Simulink blocks or reference design may have their own constraints on the number of streaming channels. But in general, this is possible.
その他の回答 (2 件)
Kiran Kintali 2021 年 11 月 1 日
編集済み: Kiran Kintali 2021 年 11 月 1 日
Getting Started with AXI4-Stream Interface in Zynq Workflow
This example shows how to use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq hardware
Your usecase seems different, but this example seems relevant for the topic
FM Broadcast Receiver
This example shows how to build an FM mono or stereo receiver using Simulink® and Communications Toolbox™. You can either use captured signals, or receive signals in real time using the RTL-SDR or ADALM-PLUTO.