HDL Resource Untilization does not match Synthsis Ouput

When running hdl coder for example on mlhdlc_sobelfilter.m the utilization report says the hdl needs multipliers (90) adders/Subtractors (131) etc. Running it through Quartus there are no multipliers or adders. Looking at the generated verilog it appears that Workflow Advisor is incorrectly assuming 32x32 bit adders etc for things which are trivially optimized away. In more complex designs this report becomes useless and one has to run through quartus/ise with each iteration of the m code to get a real picture of the utilization. Is there a switch or setting which will eliminate this issue.

Answer 1

[Tim McBrayer]

The short answer: no, there is no such setting.

The resource reporting in HDL Coder correlates strongly with a textual analysis of the output HDL code. As HDL Coder is not a synthesis tool it has no real way to know what will ultimately be realized onto the FPGA. The resource report can be used to see the relative change in usage between HDL Coder runs.