SPICE PMOS

SPICE-compatible P-Channel MOSFET

Libraries:
Simscape / Electrical / Additional Components / SPICE Semiconductors

Description

The SPICE PMOS block represents a SPICE-compatible positive-channel (P-Channel) metal-oxide semiconductor (MOS) field-effect transistor (FET). If the gate-source voltage decreases, the channel conductance increases. If the gate-source voltage is increased, the channel conductance decreases.

SPICE, or Simulation Program with Integrated Circuit Emphasis, is a simulation tool for electronic circuits. You can convert some SPICE subcircuits into equivalent Simscape™ Electrical™ models using the Environment Parameters block and SPICE-compatible blocks from the Additional Components library. For more information, see subcircuit2ssc.

Equation Variables

Variables for the SPICE PMOS block equations include:

Variables that you define by specifying parameters for the SPICE PMOS block. The visibility of some of the parameters depends on the value that you set for other parameters. For more information, see Parameters.
Geometry-adjusted variables, which depend on several of the values that you specify using parameters for the SPICE PMOS block. For more information, see Geometry-Adjusted Variables.
Temperature, T, which is 300.15 K by default. You can use a different value by specifying parameters for the SPICE PMOS block or by specifying parameters for both the SPICE PMOS block and an Environment Parameters block. For more information, see Transistor Temperature.
Minimal conductance, GMIN, which is 1e-12 1/Ohm by default. You can use a different value by specifying a parameter for an Environment Parameters block. For more information, see Minimal Conduction.
Thermal voltage, V_tn. For more information, see Thermal Voltage.

Geometry-Adjusted Variables

Several variables in the equations for the SPICE P-channel MOSFET model consider the geometry of the device that the block represents. These geometry-adjusted variables depend on variables that you define by specifying SPICE PMOS block parameters. The geometry-adjusted variables depend on these variables:

AREA — Area of the device
SCALE — Number of parallel connected devices
The associated unadjusted variable

The table includes the geometry-adjusted variables and the defining equations.

Variable	Description	Equation
KP_d	Geometry-adjusted transconductance	$K P_{d} = K P * A R E A * S C A L E$
IS_d	Geometry-adjusted bulk saturation current	$I S_{d} = I S * A R E A * S C A L E$
JS_d	Geometry-adjusted bulk junction saturation current density	$J S_{d} = J S * A R E A * S C A L E$
CBD_d	Geometry-adjusted zero-bias bulk-drain capacitance	$C B D_{d} = C B D * A R E A * S C A L E$
CBS_d	Geometry-adjusted zero-bias bulk-source capacitance	$C B S_{d} = C B S * A R E A * S C A L E$
CGSO_d	Geometry-adjusted gate-source overlap capacitance	$C G S O_{d} = C G S O * A R E A * S C A L E$
CGDO_d	Geometry-adjusted gate-drain overlap capacitance	$C G D O_{d} = C G D O * A R E A * S C A L E$
CGBO_d	Geometry-adjusted gate-bulk overlap capacitance	$C G B O_{d} = C G B O * A R E A * S C A L E$
CJ	Geometry-adjusted bottom capacitance per junction area	$C J_{d} = C J * A R E A * S C A L E$
CJSW	Geometry-adjusted sidewall capacitance per junction perimeter	$C J S W_{d} = C J S W * A R E A * S C A L E$
RD_d	Geometry-adjusted drain resistance	$R D_{d} = \frac{R D}{A R E A * S C A L E}$
RS_d	Geometry-adjusted source resistance	$R S_{d} = \frac{R S}{A R E A * S C A L E}$
RSH_d	Geometry-adjusted sheet resistance	$R S H_{d} = \frac{R S H}{A R E A * S C A L E}$

Transistor Temperature

There are two different options for defining transistor temperature, T:

Fixed temperature — The block uses a temperature that is independent of the circuit temperature when the Model temperature dependence using parameter in the Temperature settings of the SPICE PMOS block is set to Fixed temperature. For this model, the block sets T equal to TFIXED.
Device temperature — The block uses a temperature that depends on circuit temperature when the Model temperature dependence using parameter in the Temperature settings of the SPICE PMOS block is set to Device temperature. For this model, the block defines temperature as

$T = T_{C} + T O F F S E T$
Where:
- T_C is the circuit temperature.
  If there is not an Environment Parameters block in the circuit, T_C is equal to 300.15 K.
  If there is an Environment Parameters block in the circuit, T_C is equal to the value that you specify for the Temperature parameter in the SPICE settings of the Environment Parameters block. The default value for the Temperature parameter is 300.15 K.
- TOFFSET is the offset local circuit temperature.

Minimal Conduction

Minimal conductance, GMIN, has a default value of 1e–12 1/Ohm. To specify a different value:

If there is not already an Environment Parameters block in the circuit, add one.
In the SPICE settings of the Environment Parameters block, specify the desired GMIN value for the GMIN parameter.

Thermal Voltage

V_tn is the thermal voltage, which is defined as

$V_{t n} = N \frac{k * T}{q}$

Where:

N is the emission coefficient.
T is the transistor temperature. For more information, see Transistor Temperature.
k is the Boltzmann constant.
q is the elementary charge on an electron.

Parameters Calculations

The tables show how the SPICE PMOS block determines some of its parameters based on values that you specify.

Drain Resistance

Parameter Values			Geometry-Adjusted Transistor Drain Resistance
Drain resistance, RD	Sheet resistance, RSH	Number of drain squares, NRD	Geometry-Adjusted Transistor Drain Resistance
`NaN`	`NaN`	`NaN`	0
`NaN`	RSH	`NaN`	0
`NaN`	`NaN`	NRD	0
RD	`NaN` or RSH	`NaN` or NRD	RD_d
`NaN`	RSH	NRD	RSH_d*NRD

Source Resistance

Parameter Values			Geometry-Adjusted Transistor Source Resistance
Source resistance, RS	Sheet resistance, RSH	Number of source squares, NRS	Geometry-Adjusted Transistor Source Resistance
`NaN`	`NaN`	`NaN`	0
`NaN`	RSH	`NaN`	0
`NaN`	`NaN`	NRS	0
RS	`NaN` or RSH	`NaN` or NRS	RS_d
`NaN`	RSH	NRS	RSH_d*NRS

Transconductance and Surface Mobility

Parameter Values			Geometry-Adjusted Transconductance (level 1), in A/V²	Geometry-Adjusted Transconductance (level 3), in A/V²	Surface mobility (level 3), in cm²/s/V
Oxide thickness, TOX	Surface mobility, U0	Transconductance, KP	Geometry-Adjusted Transconductance (level 1), in A/V²	Geometry-Adjusted Transconductance (level 3), in A/V²	Surface mobility (level 3), in cm²/s/V
`NaN`	`NaN`	`NaN`	`2e-5` (default value)	`2e-5` (default value)	`600` (default value)
`NaN`	`NaN`	`KP`	`KP_d`	`KP_d`	`600`
`NaN`	`U0`	`NaN`	`2e-5`	UO*EPXox/`1e-7`	`U0`
`NaN`	`U0`	`KP`	`KP_d`	`KP_d`	`U0`
TOX	`NaN`	`NaN`	`600`*EPXox/TOX	`600`*EPXox/TOX	`600`
TOX	`NaN`	`KP`	`KP_d`	`KP_d`	`600`
TOX	`U0`	`NaN`	UO*EPXox/TOX	UO*EPXox/TOX	`U0`
TOX	`U0`	`KP`	`KP_d`	`KP_d`	`U0`

Oxide Thickness and Threshold Voltage

Parameter Values				Surface potential, PHI (level 1), in V	Threshold voltage, VTO (level 1), in V	Surface potential, PHI (level 3), in V	Threshold voltage, VTO (level 3), in V
Oxide thickness, TOX	Substrate doping, NSUB	Surface potential, PHI	Threshold voltage, VTO	Surface potential, PHI (level 1), in V	Threshold voltage, VTO (level 1), in V	Surface potential, PHI (level 3), in V	Threshold voltage, VTO (level 3), in V
`NaN`	`NaN`	`NaN`	`NaN`	`0.6` (default value)	0 (default value)	`0.6` (default value)	0 (default value)
`NaN`	`NaN`	`NaN`	`VTO`	`0.6`	`VTO`	`0.6`	`VTO`
`NaN`	`NaN`	`PHI`	`NaN`	`PHI`	0	`PHI`	0
`NaN`	`NaN`	`PHI`	`VTO`	`PHI`	`VTO`	`PHI`	`VTO`
`NaN`	`NSUB`	`NaN`	`NaN`	`0.6`	0	`PHI (1e-7, NSUB)`	`VTO (1e-7, NSUB)`
`NaN`	`NSUB`	`NaN`	`VTO`	`0.6`	`VTO`	`PHI (1e-7, NSUB)`	`VTO`
`NaN`	`NSUB`	`PHI`	`NaN`	`PHI`	0	`PHI`	`VTO (1e-7, NSUB)`
`NaN`	`NSUB`	`PHI`	`VTO`	`PHI`	`VTO`	`PHI`	`VTO`
`TOX`	`NaN`	`NaN`	`NaN`	`0.6`	0	`0.6`	0
`TOX`	`NaN`	`NaN`	`VTO`	`0.6`	`VTO`	`0.6`	`VTO`
`TOX`	`NaN`	`PHI`	`NaN`	`PHI`	0	`PHI`	0
`TOX`	`NaN`	`PHI`	`VTO`	`PHI`	`VTO`	`PHI`	`VTO`
`TOX`	`NSUB`	`NaN`	`NaN`	`PHI (NSUB, TOX)`	`VTO (NSUB, TOX)`	`PHI (NSUB, TOX)`	`VTO (NSUB, TOX)`
`TOX`	`NSUB`	`NaN`	`VTO`	`PHI (NSUB, TOX)`	`VTO`	`PHI (NSUB, TOX)`	`VTO`
`TOX`	`NSUB`	`PHI`	`NaN`	`PHI`	`VTO (NSUB, TOX)`	`PHI`	`VTO (NSUB, TOX)`
`TOX`	`NSUB`	`PHI`	`VTO`	`PHI`	`VTO`	`PHI`	`VTO`

Where PHI (NSUB, TOX), PHI (1e-7, NSUB), VTO (NSUB, TOX), and VTO (1e-7, NSUB) are obtained using these equations:

$P H I = 2 \frac{k T}{q} \ln (\frac{N S U B}{n i})$

$G A M M A = \frac{\sqrt{2 q ε_{s i} N S U B}}{C_{o x}}$

$\begin{array}{l} V_{F B} = φ_{M S} - \frac{q N S S}{C_{o x}} \\ V_{T_{O}} = V_{F B} - P H I - G A M M A * \sqrt{P H I} . \end{array}$

Bulk-Source Diode Model

The table shows the equations that define the relationship between the source-bulk current, I_sb, and voltage, V_sb. As applicable, the model parameters are first adjusted for temperature. For more information, see Temperature Dependence.

Applicable Range of V_sb Values	Corresponding I_gs Equation
$V_{s b} > 80 * V_{t n}$	$I_{s b} = I S_{s b} * ((\frac{V_{s b}}{V_{t n}} - 79) e^{80} - 1) + V_{s b} * G \min$
$80 V_{t n} \geq V_{s b}$	$I_{s b} = I S_{s b} * (e^{V_{s b} / V_{t n}} - 1) + V_{s b} * G \min$

Where:

IS_sb is the bulk saturation current, such that, if:
- $J S_{d} \neq 0$ and $A S \neq 0$ , $I S_{s b} = J S_{d} * A S$ .
  Where:
  - JS_d is the geometry-adjusted bulk junction saturation current density.
  - AS is the source area.
- If $J S_{d} = 0$ or $A S = 0$ , $I S_{s b} = I S_{d}$ , where IS_d is the geometry-adjusted bulk saturation current.
V_tn is the thermal voltage. For more information, see Thermal Voltage.
G_min is the minimal conductance. For more information, see Minimal Conduction.

Bulk-Drain Diode Model

The table shows the equations that define the relationship between the drain-bulk current, I_db, and voltage, V_db. As applicable, the model parameters are first adjusted for temperature. For more information, see Temperature Dependence.

Applicable Range of V_db Values	Corresponding I_db Equation
$V_{d b} > 80 * V_{t n}$	$I_{d b} = I S_{d b} * ((\frac{V_{d b}}{V_{t n}} - 79) e^{80} - 1) + V_{d b} * G \min$
$80 V_{t n} \geq V_{d b}$	$I_{d b} = I S_{d b} * (e^{V_{d b} / V_{t n}} - 1) + V_{d b} * G \min$

Where:

IS_db is the bulk drain current, such that:
- If $J S_{d} \neq 0$ and $A D \neq 0$ , $I S_{d b} = J S_{d} * A D$ .
  Where:
  - JS_d is the geometry-adjusted bulk junction saturation current density.
  - AD is the drain area.
- If $J S_{d} = 0$ or $A D = 0$ , $I S_{d b} = I S_{d}$ , where IS_d is the geometry-adjusted bulk saturation current.
V_tn is the thermal voltage. For more information, see Thermal Voltage.
G_min is the minimal conductance. For more information, see Minimal Conduction.

Level 1 Drain Current Model

This table shows relationship between the drain current I_sd and the source-drain voltage V_sd in normal mode (V_sd ≥ 0). As applicable, model parameters are first adjusted for temperature.

Normal Mode

Applicable Range of V_sg and V_sd Values	Corresponding I_sd Equation
$V_{s g} - V_{o n} \leq 0$	$I_{s d} = 0$
$0 < V_{s g} - V_{o n} \leq V_{s d}$	$I_{s d} = B E T A * {(V_{s g} - V_{o n})}^{2} \frac{(1 + L A M B D A * V_{s d})}{2}$
$0 < V_{s d} < V_{s g} - V_{o n}$	$\begin{matrix} I_{s d} = B E T A * \\ V_{s d} ((V_{s g} - V_{o n}) - \frac{V_{s d}}{2}) (1 + L A M B D A * V_{s d}) \end{matrix}$

Where:

V_on depends on V_sb and PHI.

Applicable Relationship of V_sb and PHI Values	Corresponding V_on Equation
$V_{s b} \leq 0$	$V_{o n} = M T Y P E * V B I + G A M M A \sqrt{P H I - V_{s b}}$
$0 < V_{s b} \leq 2 * P H I$	$V_{o n} = M T Y P E * V B I + G A M M A (\sqrt{P H I} - \frac{V_{s b}}{2 \sqrt{P H I}})$
$V_{s b} > 2 * P H I$	$V_{o n} = M T Y P E * V B I$

MTYPE is -1.
BETA is $B E T A = (K P_{d} * W I D T H) / (L E N G T H - 2 * L D)$
KP is:
- The Transconductance, KP, if this parameter has a numerical value.
- $U 0 * 3.9 * ε_{0} / T O X$ , if Transconductance, KP is NaN and you specify values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters.
WIDTH is the channel width.
LENGTH is the channel length.
LD is the lateral diffusion.
VBI is a built-in voltage value the block uses in calculations. The value is a function of temperature. For a detailed definition, see Temperature Dependence.
PHI is:
- The Surface potential, PHI, if this parameter has a numerical value.
- $2 * k T_{m e a s} / q * \log (N S U B / n_{i})$ , if Surface potential, PHI is NaN and you specify values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters.
LAMBDA is the channel modulation.
GAMMA is:
- The Bulk threshold, GAMMA, if this parameter has a numerical value.
- $T O X * \sqrt{2 * 11.7 * ε_{0} * q * N S U B} / (3.9 * ε_{0})$ , if Bulk threshold, GAMMA is NaN and you specify values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters.
ε₀ is the permittivity of free space, 8.854214871e-12 F/m.
n_i is the carrier concentration of intrinsic silicon, 1.45e10 cm^-3.

This table shows relationship between the drain current I_sd and the source-drain voltage V_sd in inverse mode (V_sd < 0). As applicable, model parameters are first adjusted for temperature.

Inverse Mode

Applicable Range of V_dg and V_sd Values	Corresponding I_sd Equation
$V_{d g} - V_{o n} \leq 0$	$I_{s d} = 0$
$0 < V_{d g} - V_{o n} \leq - V_{s d}$	$I_{s d} = - B E T A {(V_{d g} - V_{o n})}^{2} (1 - L A M B D A * V_{s d}) / 2$
$0 < - V_{s d} < V_{d g} - V_{o n}$	$\begin{matrix} I_{s d} = B E T A * \\ V_{s d} ((V_{d g} - V_{o n}) + V_{s d} / 2) (1 - L A M B D A * V_{s d}) \end{matrix}$

V_on depends on V_db and PHI.

Applicable Relationship of V_db and PHI Values	Corresponding V_on Equation
$V_{d b} \leq 0$	$V_{o n} = M T Y P E * V B I + G A M M A \sqrt{P H I - V_{d b}}$
$0 < V_{d b} \leq 2 * P H I$	$V_{o n} = M T Y P E * V B I + G A M M A (\sqrt{P H I} - \frac{V_{d b}}{2 \sqrt{P H I}})$
$V_{d b} > 2 * P H I$	$V_{o n} = M T Y P E * P H I$

Level 3 Drain Current Model

The block provides the following model for drain current I_sd in normal mode ( $V_{s d} \geq 0$ ) after adjusting the applicable model parameters for temperature.

$I_{S D} = I_{S D 0} * S c a l e_{V M A X} * S c a l e_{L C h a n} * S c a l e_{I N V}$

Where:

I_DS0 is the Basic Drain Current Model.
Scale_VMAX is the Velocity Saturation Scaling.
Scale_LChan is the Channel Length Modulation Scaling.
Scale_INV is the Weak Inversion Scaling.

The block uses the same model for drain current in inverse mode ( $V_{s d} < 0$ ), with the following substitutions:

$V_{s b} \equiv V_{s b} - V_{s d}$
$V_{s g} \equiv V_{s g} - V_{s d}$
$V_{s d} \equiv - V_{s d}$

Basic Drain Current Model

The relationship between the drain current I_sd and the source-drain voltage V_sd is

$I_{S D 0} = B E T A * F_{g a t e} * (V_{S G X} - V_{T H} - \frac{1 + F_{B}}{2} * V_{S D X}) * V_{S D X}$

Where:

BETA is calculated as described in Level 1 Drain Current Model.
F_GATE is calculated as

$F_{g a t e} = \frac{1}{1 + T H E T A * (V_{s g x} - V_{T H})}$
Where:
- THETA models the dependence of the mobility on the gate-source voltage.
- $V_{s g x} = \max (V_{S G}, V_{o n})$
If you specify a nonzero value for the Fast surface state density, NFS parameter, the block calculates V_on using this equation:

$V_{o n} = V_{T H} + x_{n} V_{T}$
Otherwise,

$V_{o n} = V_{T H}$
The block calculates x_n as

$x_{n} = 1 + \frac{q * N F S}{C O X} + \frac{(G A M M A * F_{s} * \sqrt{V_{b u l k}} + \frac{F_{n} * V_{b u l k}}{W I D T H})}{2 * V_{b u l k}}$
The block calculates V_bulk as follows:
- If
  
  $V_{S B} \leq 0,$
  
  $V_{b u l k} = P H I - V_{S B} .$
- Otherwise, the block calculates V_bulk as
  
  $V_{b u l k} = \frac{P H I}{{(1 + \frac{V_{S B}}{2 * P H I})}^{2}}$
Thermal voltage such that

$V_{T} = \frac{k T}{q}$
The block calculates V_TH using the following equation:

$\begin{array}{l} V_{T H} = V_{B I} - \frac{8.15 e^{- 22} * E T A}{C O X * {(L E N G T H - 2 * L D)}^{3}} * V_{S D} \\ + G A M M A * F_{s} * \sqrt{V_{b u l k}} + F_{n} * V_{b u l k} \end{array}$
For information about how the block calculates V_BI, see Temperature Dependence.
ETA is the Vds dependence threshold volt, ETA.
$C O X = \frac{ε_{o x}}{T O X},$
Where ε_ox is the permittivity of the oxide and TOX is the Oxide thickness, TOX.
If you specify a nonzero value for the Junction depth, XJ parameter and a value for the Substrate doping, NSUB parameter, the block calculates F_s using these equations:

$α = \frac{2 ε_{s i}}{q N S U B}$

$X D = \sqrt{α}$

$w c = .0631353 + .8013292 * \frac{X D * \sqrt{V_{b u l k}}}{X J} - .01110777 * {(\frac{X D * \sqrt{V_{b u l k}}}{X J})}^{2} + \frac{L D}{X J}$

$F_{s} = 1 - (w c * {\sqrt{1 - (\frac{X D * \sqrt{V_{b u l k}}}{X J + X D * \sqrt{V_{b u l k}}})}}^{2} - \frac{L D}{X J})$
Where ε_si is the permittivity of silicon.
Otherwise,

$F_{s} = 1$
The block calculates F_B as

$F_{B} = \frac{G A M M A * F_{s}}{4 * \sqrt{V_{b u l k}}} + F_{n}$
The block calculates F_n as

$F_{n} = \frac{D E L T A * π * ε_{s i}}{2 * C O X * W I D T H}$
DELTA is the width effect on threshold.
V_SDX is the lesser of V_SD and the saturation voltage, V_dsat.
- If you specify a positive value for the Max carrier drift velocity, VMAX parameter, the block calculates V_dsat using the following equation:
  
  $\begin{array}{l} V_{d s a t} = \frac{V_{s g x} - V_{T H}}{1 + F_{B}} + \frac{(L E N G T H - 2 * L D) * V M A X}{U O * F_{g a t e}} \\ - \sqrt{{(\frac{V_{s g x} - V_{T H}}{1 + F_{B}})}^{2} + {(\frac{(L E N G T H - 2 * L D) * V M A X}{U O * F_{g a t e}})}^{2}} \end{array}$
  Otherwise, the block calculates V_dsat as
  
  $V_{d s a t} = \frac{V_{s g x} - V_{T H}}{1 + F_{B}}$

Velocity Saturation Scaling

If you specify a positive value for the Max carrier drift velocity, VMAX parameter, the block calculates Scale_VMAX as

$S c a l e_{V M A X} = \frac{1}{1 + \frac{U O * F_{g a t e}}{(L E N G T H - 2 * L D) * V M A X} * V_{S D X}}$

Otherwise,

$S c a l e_{V M A X} = 1$

Channel Length Modulation Scaling

The block scales the drain current to account for channel length modulation if $V_{S D} > V {}_{d s a t}$ and the Max carrier drift velocity, VMAX is less than or equal to zero or α is nonzero.

The block scales the drain current using the following equation:

$S c a l e_{L C h a n} = \frac{1}{1 - \frac{Δ l}{(L E N G T H - 2 * L D)}}$

To calculate $Δ l$ the block:

Calculates the intermediate value $Δ l_{0}$ .
- If you specify a positive value for the Max carrier drift velocity, VMAX parameter, the block computes the intermediate value g_dsat as the greater of 1e-12 and the result of the following equation:
  
  $I_{S D 0} * (1 - \frac{1}{1 + S c a l e_{g_{d s a t}} * V_{S D X}}) * S c a l e_{g_{d s a t}}$
  Where:
  
  $S c a l e_{g_{d s a t}} = \frac{U O * F_{g a t e}}{(L E N G T H - 2 * L D) * V M A X}$
  Then, the block uses the following equation to calculate the intermediate value Δl₀:
  
  $\begin{array}{l} Δ l_{0} = \sqrt{{(\frac{K A * I_{S D}}{2 * (L E N G T H - 2 * L D) * g_{d s a t}})}^{2} + K A * (V_{S D} - V_{d s a t})} \\ - \frac{K A * I_{S D}}{2 * (L E N G T H - 2 * L D) * g_{d s a t}} \end{array}$
  Where
  
  $K A = K A P P A * α .$
- Otherwise, the block uses the following equation to calculate the intermediate value $Δ l_{0}$ as
  
  $Δ l = \sqrt{K A * (V_{S D} - V_{d s a t})}$
The block checks for punch through and calculates $Δ l$ .
- If
  
  $Δ l_{0} > (L E N G T H - 2 * L D) / 2,$
  the block calculates $Δ l$ using the following equation:
  
  $Δ l = (1 - \frac{(L E N G T H - 2 * L D)}{4 * Δ l_{0}}) * (L E N G T H - 2 * L D)$
- Otherwise,
  
  $Δ l = Δ l_{0} .$

Weak Inversion Scaling

If V_SG is less than V_on, the block calculates Scale_INV using the following equation:

$S c a l e_{I N V} = e^{\frac{V_{s g} - V_{o n}}{x_{n} * V_{T}}}$

Otherwise,

$S c a l e_{I N V} = 1$

Junction Charge Model

The block models the Junction Overlap Charges and the Bulk Junction Charges.

Junction Overlap Charges

The block calculates the following junction overlap charges:

$Q_{S G} = C G S O_{d} * W I D T H * V_{s g}$

Where:
- Q_SG is the source-gate overlap charge.
- CGSO_d is the geometry adjusted gate-source overlap capacitance.
- WIDTH is the channel width.
$Q_{D G} = C G D O_{d} * W I D T H * V_{d g}$

Where:
- Q_DG is the drain-gate overlap charge.
- CGDO_d is the geometry adjusted gate-drain overlap capacitance.
$Q_{B G} = C G B O_{d} * (L E N G T H - 2 * L D) * V_{b g}$

Where:
- Q_BG is the bulk-gate overlap charge.
- CGBO_d is the geometry adjusted gate-bulk overlap capacitance.
- LENGTH is the channel length.
- LD is the lateral diffusion.

Bulk Junction Charges

This table shows relationship between the bulk-drain bottom junction charge Q_bottom and the junction voltage, V_db. As applicable, model parameters are first adjusted for temperature.

Applicable Range of V_db Values	Corresponding Q_bottom Equation
$V_{d b} < F C * P B$	$Q_{b o t t o m} = \frac{C B D_{d} * P B * (1 - {(1 - \frac{V_{d b}}{P B})}^{1 - M J})}{1 - M J}$ if CBD > 0. $Q_{b o t t o m} = \frac{C J_{d} * A D * P B * (1 - {(1 - \frac{V_{d b}}{P B})}^{1 - M J})}{1 - M J}$ otherwise.
$V_{d b} \geq F C * P B$	$\begin{array}{l} Q_{b o t t o m} = C B D_{d} * \\ (F 1 + \frac{F 3 * (V_{d b} - F C * P B) + \frac{M J * (V_{d b}^{2} - {(F C * P B)}^{2})}{2 * P B}}{F 2}) \end{array}$ if $C B D_{d} > 0$ . $\begin{array}{l} Q_{b o t t o m} = C J_{d} * A D * \\ (F 1 + \frac{F 3 * (V_{d b} - F C * P B) + \frac{M J * (V_{d b}^{2} - {(F C * P B)}^{2})}{2 * P B}}{F 2}) \end{array}$ otherwise.

Applicable Range of V_db Values

Corresponding Q_bottom Equation

V_{d b} < F C * P B

$Q_{b o t t o m} = \frac{C B D_{d} * P B * (1 - {(1 - \frac{V_{d b}}{P B})}^{1 - M J})}{1 - M J}$ if CBD > 0.

$Q_{b o t t o m} = \frac{C J_{d} * A D * P B * (1 - {(1 - \frac{V_{d b}}{P B})}^{1 - M J})}{1 - M J}$ otherwise.

V_{d b} \geq F C * P B

$\begin{array}{l} Q_{b o t t o m} = C B D_{d} * \\ (F 1 + \frac{F 3 * (V_{d b} - F C * P B) + \frac{M J * (V_{d b}^{2} - {(F C * P B)}^{2})}{2 * P B}}{F 2}) \end{array}$ if $C B D_{d} > 0$ .

$\begin{array}{l} Q_{b o t t o m} = C J_{d} * A D * \\ (F 1 + \frac{F 3 * (V_{d b} - F C * P B) + \frac{M J * (V_{d b}^{2} - {(F C * P B)}^{2})}{2 * P B}}{F 2}) \end{array}$

otherwise.

Where:

PB is the bulk junction potential.
FC is the capacitance coefficient.
CBD_d is the geometry-adjusted zero-bias bulk-drain capacitance.
CJ_d is the geometry-adjusted bottom capacitance per junction area.
AD is the drain area.
MJ is the bottom grading coefficient.
$F 1 = \frac{P B * (1 - {(1 - F C)}^{1 - M J})}{1 - M J}$
$F 2 = {(1 - F C)}^{1 + M J}$
$F 3 = 1 - F C * (1 + M J)$

To calculate the bulk-source bottom junction charge, the block substitutes variables in the equations in the preceding table. The block substitutes:

V_sb replaces V_db.
AS for AD
CBS_d for CBD_d

This table shows relationship between the bulk-drain sidewall junction charge Q_sidewall and the junction voltage V_db. As applicable, model parameters are first adjusted for temperature.

Applicable Range of V_db Values	Corresponding Q_sidewall Equation
$V_{d b} < F C * P B$	$Q_{s i d e w a l l} = \frac{C J S W_{d} * P D * P B * (1 - {(1 - \frac{V_{d b}}{P B})}^{1 - M J S W})}{1 - M J S W}$
$V_{d b} \geq F C * P B$	$\begin{array}{l} Q_{s i d e w a l l} = C J S W_{d} * P D * \\ (F 1 + \frac{F 3 * (V_{d b} - F C * P B) + \frac{M J S W * (V_{d b}^{2} - {(F C * P B)}^{2})}{2 * P B}}{F 2}) \end{array}$

Where:

CJSW_d is the geometry adjusted sidewall capacitance per junction perimeter.
PD is the drain perimeter.
MGSW is the side grading coefficient.
$F 1 = \frac{P B * (1 - {(1 - F C)}^{1 - M J S W})}{1 - M J S W}$
$F 2 = {(1 - F C)}^{1 + M J S W}$
$F 3 = 1 - F C * (1 + M J S W)$

To calculate the bulk-source sidewall junction charge and the sidewall junction voltage, the block substitutes variables in the equations in the preceding table. The block substitutes:

V_sb replaces V_db.
PS for PD

Capacitance Model

The SPICE PMOS block allows you to model the transistor capacitance model in three different ways:

Meyer Gate Capacitance Model

This table shows the relationship between the operational regions of the transistor and the gate-bulk, gate-drain, and gate-source capacitances.

Operational region	Gate-Bulk, C_gb, Gate-Drain, C_gd, and Gate-Source, C_gs, Equations
Accumulation region, $V_{g b} < V_{F B}$	$\begin{array}{l} C_{g b} = C o x t \\ C_{g d} = 0 \\ C_{g s} = 0 \end{array}$
Depletion region, $V_{g s} < V_{T H}$	$\begin{array}{l} C_{g b} = \frac{C o x t}{\sqrt{1 + \frac{4}{G A M M A^{2}} * (V_{g b} - V_{F B})}} \\ C_{g d} = 0 \\ C_{g s} = 0 \end{array}$
Saturation region, $V_{g s} - V_{T H} < V_{d s}$	if $V_{d s} < V_{s a t m i n}$ then:	if $V_{d s} \geq V_{s a t m i n}$ then:
Saturation region, $V_{g s} - V_{T H} < V_{d s}$	$\begin{array}{l} C_{g b} = 0 \\ C_{g d} = \frac{2}{3} (C o x t - C_{g b}) (1 - \frac{{(V_{s a t m i n})}^{2}}{{(2 V_{s a t m i n} - V_{d s})}^{2}}) \\ C_{g s} = \frac{2}{3} (C o x t - C_{g b}) (1 - \frac{{(V_{s a t m i n} - V_{d s})}^{2}}{{(2 V_{s a t m i n} - V_{d s})}^{2}}) \end{array}$	$\begin{array}{l} C_{g b} = 0 \\ C_{g d} = 0 \\ C_{g s} = \frac{2}{3} (C o x t - C_{g b}) \end{array}$
Linear region, $V_{g s} - V_{T H} > V_{d s}$	$\begin{array}{l} C_{g b} = 0 \\ C_{g d} = \frac{2}{3} (C o x t - C_{g b}) * (1 - \frac{{(V_{g s} - V_{T H})}^{2}}{{(2 * (V_{g s} - V_{T H}) - V_{d s})}^{2}}) \\ C_{g s} = \frac{2}{3} (C o x t - C_{g b}) * (1 - \frac{{(V_{g s} - V_{T H} - V_{d s})}^{2}}{{(2 * (V_{g s} - V_{T H}) - V_{d s})}^{2}}) \end{array}$

where:

$C o x t = W I D T H * (L E N G T H - 2 * L D) * C O X * A R E A * S C A L E$
$V_{F B} = V B I * M T Y P E - P H I$ is the flat-band voltage.
V_satmin is the minimum saturation voltage. It is a predefined parameter equal to 1 V.

These equations are continuous between the depletion region and the accumulation region, and discontinuous between the depletion and the inversion region. Other SPICE tools apply smoothing functions between the inversion and depletion regions.

$\begin{array}{l} C_{g b} = \frac{W I D T H * L E N G T H * C O X}{\sqrt{{(1 + \frac{4}{G A M M A^{2}} * (V_{T H} - V_{b s} - V_{F B}))}^{m}}} * s m o o t h i n g \\ s m o o t h i n g = \frac{1}{{(1 + \frac{4}{G A M M A^{2}} * (V_{g s} - V_{T H}))}^{m}} \end{array}$

where m is a predefined smoothing constant.

Charge Conservation Capacitance Model

This table shows the relationship between the operational regions of the transistor and the gate, bulk, channel, drain, and source charges for a level 1 MOS.

Operational region	Level-1 Charges Equations
Accumulation region, $V_{g b} < V_{F B}$	$\begin{array}{l} Q_{g} = C o x t * (V_{g b} - V_{F B}) \\ Q_{b} = - C o x t * (V_{g b} - V_{F B}) \\ Q_{c} = 0 \\ Q_{d} = 0 \\ Q_{s} = Q_{c} - Q_{d} \end{array}$
Depletion region, $V_{g s} < V_{T H}$	$\begin{array}{l} Q_{g} = - 0.5 * C o x t * G A M M A^{2} * (1 - \sqrt{1 + \frac{4}{G A M M A^{2}} * (V_{g b} - V_{F B})}) \\ Q_{b} = 0.5 * C o x t * G A M M A^{2} * (1 - \sqrt{1 + \frac{4}{G A M M A^{2}} * (V_{g b} - V_{F B})}) \\ Q_{c} = 0 \\ Q_{d} = 0 \\ Q_{s} = Q_{c} - Q_{d} \end{array}$
Saturation region, $V_{g s} - V_{T H} < V_{d s}$	$\begin{array}{l} Q_{g} = C o x t * (V_{g s} - V_{F B} - P H I - \frac{V_{g s} - V_{T H}}{3}) \\ Q_{b} = - C o x t * (V_{T H} - V_{F B} - P H I) \\ Q_{c} = - C o x t * (V_{g s} - V_{T H} - \frac{V_{g s} - V_{T H}}{3}) \\ Q_{d} = 0 \\ Q_{s} = Q_{c} - Q_{d} \end{array}$
Linear region, $V_{g s} - V_{T H} > V_{d s}$	$\begin{array}{l} Q_{g} = C o x t * (V_{g s} - V_{F B} - P H I - \frac{V_{d s}}{2} + \frac{V_{d s}^{2}}{12 (V_{g s} - V_{T H} - 0.5 V_{d s})}) \\ Q_{b} = - C o x t * (V_{T H} - V_{F B} - P H I) \\ Q_{c} = - C o x t * (V_{g s} - V_{T H} - \frac{V_{d s}}{2} + \frac{V_{d s}^{2}}{12 (V_{g s} - V_{T H} - 0.5 V_{d s})}) \\ Q_{d} = - C o x t * (\frac{V_{g s} - V_{T H}}{2} - \frac{3 V_{d s}}{4} + \frac{V_{d s}^{2}}{8 (V_{g s} - V_{T H} - 0.5 V_{d s})}) \\ Q_{s} = Q_{c} - Q_{d} \end{array}$

where:

Q_g is the gate charge.
Q_b is the bulk charge.
Q_d is the drain charge.
Q_s is the source charge.
$Q_{c} = - (Q_{g} + Q_{b}) = Q_{d} + Q_{s}$ is the charge in channel. Q_c needs to be partitioned between Q_d and Q_s.

This table shows the relationship between the operational regions of the transistor and the gate, bulk, channel, drain, and source charges for a level-3 MOS.

Operational region	Level-3 Charges Equations
Accumulation region, $V_{g b} < V_{F B}$	$\begin{array}{l} Q_{g} = C o x t * (V_{g b} - V_{F B}) - S F_{1} + S F_{2} \\ Q_{b} = - C o x t * (V_{g b} - V_{F B}) - S F_{1} + S F_{2} \\ Q_{c} = 0 \\ Q_{d} = 0 \\ Q_{s} = Q_{c} - Q_{d} \end{array}$
Depletion region, $V_{g s} < V_{T H}$	$\begin{array}{l} Q_{g} = - 0.5 * C o x t * G A M M A^{2} * (1 - \sqrt{1 + \frac{4}{G A M M A^{2}} * (V_{g b} - V_{F B})}) - S F_{1} + S F_{2} \\ Q_{b} = 0.5 * C o x t * G A M M A^{2} * (1 - \sqrt{1 + \frac{4}{G A M M A^{2}} * (V_{g b} - V_{F B})}) + S F_{1} - S F_{2} \\ Q_{c} = 0 \\ Q_{d} = 0 \\ Q_{s} = Q_{c} - Q_{d} \end{array}$
Saturation region, $V_{g s} - V_{T H} < V_{d s}$	$\begin{array}{l} Q_{g} = C o x t * (V_{g s} - V_{F B} - P H I + E T A * V_{d s a t} - \frac{V_{d s a t}}{2} + \frac{1 + F_{B}}{12 * F_{i}} * V_{d s a t}^{2}) \\ Q_{b} = - C o x t * (V_{T H} - V_{F B} - P H I + E T A * V_{d s a t} - \frac{F_{b}}{2} * V_{d s} - \frac{F_{B} * (1 + F_{B})}{12 * F_{i}} * V_{d s a t}^{2}) \\ Q_{c} = - C o x t * (V_{g s} - V_{T H} - \frac{1 + F_{B}}{2} * V_{d s a t} + \frac{{(1 + F_{B})}^{2}}{12 * F_{i}} * V_{d s a t}^{2}) \\ Q_{d} = 0 \\ Q_{s} = Q_{c} - Q_{d} \end{array}$
Linear region, $V_{g s} - V_{T H} > V_{d s}$	$\begin{array}{l} Q_{g} = C o x t * (V_{g s} - V_{F B} - P H I + E T A * V_{d s} - \frac{V_{d s}}{2} + \frac{1 + F_{B}}{12 * F_{i}} * V_{d s}^{2}) \\ Q_{b} = - C o x t * (V_{T H} - V_{F B} - P H I + E T A * V_{d s} + \frac{F_{B}}{2} * V_{d s} - \frac{F_{B} * (1 + F_{B})}{12 * F_{i}} * V_{d s}^{2}) \\ Q_{c} = - C o x t * (V_{g s} - V_{T H} - \frac{1 + F_{B}}{2} * V_{d s} + \frac{{(1 + F_{B})}^{2}}{12 * F_{i}} * V_{d s}^{2}) \\ Q_{d} = - C o x t * (\frac{V_{g s} - V_{T H}}{2} - \frac{3 (1 + F_{B})}{2} * V_{d s} + \frac{{(1 + F_{B})}^{2}}{8 * F_{i}} * V_{d s}^{2}) \\ Q_{s} = Q_{c} - Q_{d} \end{array}$

where:

V_dsat is the saturation voltage
F_B is the body effect coefficient
ETA is the drain-source voltage threshold coefficient
$F_{i} = V_{g s} - V_{T H} - \frac{1 + F_{B}}{2} * V_{d s}$
$S F_{1} = - 0.5 * C o x t * G A M M A^{2} * (1 - {(1 + \frac{4}{G A M M A^{2}} * 2 (V_{T H} - V_{b s} - V_{F B}))}^{0.5})$ and $S F_{2} = C o x t * (V_{T H} - V_{F B} - P H I)$ are smoothing factors between depletion and accumulation regions to help with convergence.

Temperature Dependence

The transconductance as a function of the transistor temperature is

$K P (T) = \frac{K P_{d}}{{(\frac{T}{T_{m e a s}})}^{3 / 2}}$

Where:

KP_d is the geometry-adjusted transconductance.
T is the transistor temperature. For more information, see Transistor Temperature.
T_meas is the parameter extraction temperature.

The surface potential as a function of the transistor temperature is

$\begin{array}{l} P H I (T) = \frac{T}{T_{m e a s}} (P H I + \frac{k T_{m e a s}}{q} (\log {(\frac{T_{m e a s}}{300.15})}^{3} + \frac{q}{k} (\frac{1.115}{300.15} - \frac{E G_{T_{m e a s}}}{T_{m e a s}}))) \\ - \frac{k T}{q} (\log {(\frac{T}{300.15})}^{3} + \frac{q}{k} (\frac{1.115}{300.15} - \frac{E G_{T}}{T})) \end{array}$

Where:

PHI is the surface potential.
k is the Boltzmann constant.
q is the elementary charge on an electron, 1.6021918e-19 C.
EG is the activation energy, such that:
- $E G_{T_{m e a s}} = 1.16 e V - (7.02 e - 4 * T_{m e a s}^{2}) / (T_{m e a s} + 1108)$
- $E G_{T} = 1.16 e V - (7.02 e - 4 * T^{2}) / (T + 1108)$

The built-in voltage as a function of the transistor temperature is

$\begin{array}{l} V B I (T) = V T O + M T Y P E * (\frac{P H I (T) - P H I}{2} - G A M M A \sqrt{P H I}) \\ + \frac{E G_{T_{m e a s}} - E G_{T}}{2} \end{array}$

Where:

VBI is the built-in voltage.
VTO is the threshold voltage. VTO depends on the value that you specify for the Threshold voltage, VTO parameter in the DC currents settings. If you specify a numerical value, VTO is evaluated as that value. If you specify a nonnumerical value (NAN) and you specify numerical values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters in the Process settings, then VTO is evaluated as $Φ - 3.25 + E G_{T_{m e a s}} / 2 + M T Y P E * P H I / 2 - N S S * q * T O X / (3.9 * ε_{0}) + M T Y P E * (G A M M A * \sqrt{P H I} + P H I)$ , Where:
- Φ depends on the gate type, which you specify using the Gate type, TPG parameter. If you specify Aluminum (0), $Φ = 3.2$ . Otherwise, $Φ = 3.25 + E G_{T_{m e a s}} / 2 - M T Y P E * T P G * E G_{T_{m e a s}} / 2$ , Where:
  - MTYPE is the transistor type. For an P-channel MOSFET, MTYPE = -1.
  - TPG represents the gate type and also depends on the option that you specify for the Gate type, TPG parameter in the Process settings. If you specify
    
    Opposite of substrate (1) — TPG = 1
    Same as substrate (-1) — TPG = -1
- NSS is the surface state density.
- TOX is the oxide thickness.
- ε₀ is the permittivity of free space.
- GAMMA is the bulk threshold. GAMMA depends on the value that you specify for the Bulk threshold, GAMMA parameter in the DC currents settings. If you specify a numerical value, GAMMA is evaluated as that value. If you specify a nonnumerical value (NAN) and you specify numerical values for both the Oxide thickness, TOX and Substrate doping, NSUB parameters in the Process settings, then VTO is evaluated as $T O X * \sqrt{2 * 11.7 * ε_{0} * q * N S U B} / (3.9 * ε_{0})$ , where NSUB is the substrate doping.

The bulk saturation current as a function of the transistor temperature is

$I S (T) = I S_{d} * e^{\frac{- q E G_{T}}{N D * k T} + \frac{q E G_{T_{m e a s}}}{N D * k T_{m e a s}}}$

Where:

IS_d is the geometry-adjusted bulk saturation current.
ND is the emission coefficient.

The bulk junction saturation current density as a function of the transistor temperature is

$J S (T) = J S_{d} * e^{\frac{- q E G_{T}}{N D * k T} + \frac{q E G_{T_{m e a s}}}{N D * k T_{m e a s}}}$

Where:

JS_d is the geometry-adjusted bulk junction saturation current density.

The bulk junction potential as a function of the transistor temperature is

$\begin{array}{l} P B (T) = \frac{P B + \frac{k T_{m e a s}}{q} (\log {(\frac{T_{m e a s}}{300.15})}^{3} + \frac{q}{k} (\frac{1.115}{300.15} - \frac{E G_{T_{m e a s}}}{T}))}{\frac{T_{m e a s}}{T}} \\ - \frac{k T}{q} (\log {(\frac{T}{300.15})}^{3} + \frac{q}{k} (\frac{1.115}{300.15} - \frac{E G_{T}}{T})) \end{array}$

Where:

PB is the bulk junction potential.

The bulk-drain junction capacitance as a function of the transistor temperature is

$C B D (T) = C B D_{d} \frac{p b o + M J * (4 * 10^{4} * (T - 300.15) * p b o - (P B (T) - p b o))}{p b o + M J * (4 * 10^{4} * (T_{m e a s} - 300.15) * p b o - (P B - p b o))}$

Where:

CBD_d is the geometry adjusted zero-bias bulk-drain capacitance.
MJ is the bottom grading coefficient.
$p b o = \frac{P B + \frac{k T_{m e a s}}{q} (\log {(\frac{T_{m e a s}}{300.15})}^{3} + \frac{q}{k} (\frac{1.115}{300.15} - \frac{E G_{T_{m e a s}}}{T}))}{\frac{T_{m e a s}}{300.15}}$

The block uses the CBD(T) equation to calculate:

The bulk-source junction capacitance by substituting CBS_d, the geometry-adjusted zero-bias bulk-source capacitance, for CBD_d.
The bottom junction capacitance by substituting CJ_d, the geometry-adjusted bottom capacitance per junction area for CBD_d.

The relationship between the sidewall junction capacitance CJSW and the transistor temperature, T, is

$C J S W (T) = C J S W_{d} \frac{p b o + M J S W * (4 * 10^{4} * (T - 300.15) * p b o - (P B (T) - p b o))}{p b o + M J S W * (4 * 10^{4} * (T_{m e a s} - 300.15) * p b o - (P B - p b o))}$

Where:

CJSW_d is the side geometry-adjusted sidewall capacitance per junction perimeter.
MJSW is the side grading coefficient.

Assumptions and Limitations

The block does not support noise analysis.
The block applies initial conditions across junction capacitors and not across the block ports.

Ports

Conserving

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gx — Gate terminal
electrical

Electrical conserving port associated with the transistor gate terminal.

dx — Drain terminal
electrical

Electrical conserving port associated with the transistor drain terminal.

sx — Source terminal
electrical

Electrical conserving port associated with the transistor source terminal.

bx — Bulk terminal
electrical

Electrical conserving port associated with the transistor bulk terminal.

Parameters

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Model Selection

MOS model — Drain current model
`Level 1 MOS` (default) | `Level 3 MOS`

MOSFET drain current model options:

Level 1 MOS — Use the Level 1 Drain Current Model. This is the default option.
Level 3 MOS — Use the Level 3 Drain Current Model.

Dependencies

The setting that you select for the MOS model affects the visibility of certain parameters in the DC Currents and Process settings.

Dimensions

Device area factor, AREA — Device area
`1.0` (default) | positive scalar

Transistor area factor for scaling. The value must be greater than 0.

Number of parallel devices, SCALE — Number of parallel devices
`1` (default) | positive integer

Number of parallel MOS instances that the block represents. This parameter multiplies the output current and device charge. The value must be greater than 0.

Length of channel, LENGTH — Source-to-drain channel length
`1e-4` `m` (default) | positive scalar

Length of the channel between the source and drain.

Width of channel, WIDTH — Source-to-drain channel width
`1e-4` `m` (default) | positive scalar

Width of the channel between the source and drain.

Area of drain, AD — Drain area
`0` `m^2` (default) | nonnegative scalar

Area of the transistor drain diffusion. The value must be greater than or equal to 0.

Area of source, AS — Source area
`0` `m^2` (default) | nonnegative scalar

Area of the transistor source diffusion. The value must be greater than or equal to 0.

Perimeter of drain, PD — Drain perimeter
`0` `m` (default) | nonnegative scalar

Perimeter of the transistor drain diffusion. The value must be greater than or equal to 0.

Perimeter of source, PS — Source perimeter
`0` `m` (default) | nonnegative scalar

Perimeter of the transistor source diffusion. The value must be greater than or equal to 0.

Resistors

Number of drain squares, NRD — Number of drain diffusion resistance squares
`0` (default) | nonnegative scalar

Number of squares of resistance that make up the transistor drain diffusion. The value must be greater than or equal to 0. The block only uses this parameter value if you do not specify one or both of the Drain resistance, RD and Source resistance, RS parameter values, as described in Parameters Calculations.

Number of source squares, NRS — Number of transistor source diffusion squares of resistance
`0` (default) | nonnegative scalar

Number of squares of resistance that make up the transistor source diffusion. The value must be greater than or equal to 0. The block only uses this parameter value if you do not specify one or both of the Drain resistance, RD and Source resistance, RS parameter values, as described in Parameters Calculations.

Drain resistance, RD — Series resistance
`0.01` `Ohm` (default) | nonnegative scalar

Transistor drain resistance. The value must be greater than or equal to 0.

Source resistance, RS — Series resistance
`0.0001` `Ohm` (default) | nonnegative scalar

Transistor source resistance. The value must be greater than or equal to 0.

Sheet resistance, RSH — Per square resistance
`0` `Ohm` (default) | nonnegative scalar

Resistance per square of the transistor source and drain. Check Parameters Calculations to see when the block uses this parameter. The value must be greater than or equal to 0.

DC Currents

Threshold voltage, VTO — Threshold voltage
`0` `V` (default) | scalar

Source-gate voltage above which the transistor produces a nonzero drain current. If you assign this parameter a value of NaN, the block calculates the value from the specified values of the Oxide thickness, TOX and Substrate doping, NSUB parameters. For more information about this calculation, see Temperature Dependence.

Transconductance, KP — Transconductance
`2e-5` `A/V^2` (default) | nonnegative scalar

Derivative of drain current with respect to gate voltage. The value must be greater than or equal to 0. If you assign this parameter a value of NaN, the block calculates the value from the specified values of the Oxide thickness, TOX and Substrate doping, NSUB parameters. For more information about this calculation, see Level 1 Drain Current Model or Level 3 Drain Current Model as appropriate for the selected value of the MOS model parameter.

Bulk threshold, GAMMA — Bulk threshold
`0` `V^0.50000` (default) | nonnegative scalar

Body effect parameter, which relates the threshold voltage, VTH, to the body bias, VBS, as described in Level 1 Drain Current Model and Level 3 Drain Current Model. The value must be greater than or equal to 0. If you assign this parameter a value of NaN, the block calculates the value from the specified values of the Oxide thickness, TOX and Substrate doping, NSUB parameters. For more information about this calculation, see Level 1 Drain Current Model or Level 3 Drain Current Model as appropriate for the selected value of the MOS model parameter.

Surface potential, PHI — Surface potential
`0.6` `V` (default) | nonnegative scalar

Twice the voltage at which the surface electron concentration becomes equal to the intrinsic concentration and the device transitions between depletion and inversion conditions. The value must be greater than or equal to 0. If you assign this parameter a value of NaN, the block calculates the value from the specified values of the Oxide thickness, TOX and Substrate doping, NSUB parameters. For more information about this calculation, see Level 1 Drain Current Model or Level 3 Drain Current Model as appropriate for the selected value of the MOS model parameter.

Channel modulation, LAMBDA — Channel-length modulation
`0` `1/V` (default) | scalar

Channel-length modulation.

Dependencies

This parameter is only visible when you select Level 1 MOS for the MOS model parameter in the Model Selection settings.

Bulk saturation current, IS — Bulk saturation current magnitude
`1e-14` `A` (default) | nonnegative scalar

Magnitude of the current that the junction approaches asymptotically for very large reverse bias levels. The value must be greater than or equal to 0.

Emission coefficient, N — Emission coefficient
`1` (default) | nonnegative scalar

Transistor emission coefficient or ideality factor. The value must be greater than 0.

Bulk jct sat current density, JS — Bulk junction saturation current density
`0` `A/m^2` (default) | nonnegative scalar

Magnitude of the current per unit area that the junction approaches asymptotically for very large reverse bias levels. The value must be greater than or equal to 0.

Width effect on threshold, DELTA — Width factor
`0` (default) | scalar

Factor that controls the effect of transistor width on threshold voltage.

Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Max carrier drift velocity, VMAX — Maximum drift velocity
`0` `m/s` (default) | scalar

Maximum drift velocity of the carriers.

Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Fast surface state density, NFS — Fast surface state density
`0` `1/cm^2` (default) | scalar

Fast surface state density adjusts the drain current for the mobility reduction caused by the gate voltage.

Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Vds dependence threshold volt, ETA — Drain-source voltage threshold
`0` (default) | scalar

Coefficient that controls how the drain voltage affects the mobility in the drain current calculation.

Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Vgs dependence on mobility, THETA — Mobility dependence coefficient
`0` `1/V` (default) | scalar

Coefficient that controls how the gate voltage affects the mobility in the drain current calculation.

Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

Mobility modulation, KAPPA — Mobility modulation coefficient
`0.2` (default) | scalar

Coefficient of channel-length modulation for the level 3 MOS model.

Dependencies

This parameter is only visible when you select Level 3 MOS for the MOS model parameter in the Model Selection settings.

C-V

Model gate capacitance (CGS, CGD, CGB) — Gate capacitance model
`No intrinsic capacitance` (default) | `Meyer gate capacitances` | `Charge conservation capacitances`

Options for modeling the gate capacitance:

No intrinsic capacitance — Do not include gate capacitance in the model.
Meyer gate capacitances — Model capacitances using Meyer gate capacitances.
Charge conservation capacitances — Model capacitances using charge conservation capacitances.

Model gate overlap capacitance (CGSO, CGDO, CGBO) — Gate overlap model
`No` (default) | `Yes`

Options for modeling the gate overlap capacitance:

No — Do not include gate overlap capacitance in the model.
Yes — Specify the gate-source, gate-drain, and gate-bulk capacitances.

Dependencies

Selecting Yes exposes related parameters.

G-S overlap capacitance, CGSO — Gate-source overlap capacitance
`0` `F/m` (default) | scalar | `0` or ≥ `1e-18`

Gate-source capacitance due to lateral diffusion of the source. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

Dependencies

This parameter is only visible when you select Yes for the Model gate overlap capacitance (CGSO, CGDO, CGBO) parameter.

G-D overlap capacitance, CGDO — Gate-drain overlap capacitance
`0` `F/m` (default) | scalar | `0` or ≥ `1e-18`

Gate-drain capacitance due to lateral diffusion of the drain. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

Dependencies

This parameter is only visible when you select Yes for the Model gate overlap capacitance (CGSO, CGDO, CGBO) parameter.

G-B overlap capacitance, CGBO — Gate-bulk overlap capacitance
`0` `F/m` (default) | scalar | `0` or ≥ `1e-18`

Gate-bulk capacitance due to gate extending beyond the channel width. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.

Dependencies

This parameter is only visible when you select Yes for the Model gate overlap capacitance (CGSO, CGDO, CGBO) parameter.

Model junction capacitance (CBD, CBS) — Junction capacitance model
`No` (default) | `Yes`

Options for modeling the junction capacitance:

No — Do not include junction capacitance in the model.
Yes — Specify zero-bias junction capacitance, junction potential, grading coefficient, forward-bias depletion and capacitance coefficient.

Dependencies

Selecting Yes exposes related parameters.

Zero-bias BD capacitance, CBD — Zero-bias junction capacitance
`0` `F` (default) | `0` or ≥ `1e-18`

Capacitance between the bulk and the drain. The value must be equal to 0 or greater than or equal to Cmin. Cmin is a built-in model constant whose value is 1e-18.