Unit Delay Enabled (Obsolete)

Delay signal one sample period, if external enable signal is on

Compatibility

Note

The Unit Delay Enabled block is not recommended. This block was removed from the Discrete library in R2016b. In new models, use the Delay block (with parameters set appropriately). Existing models that contain the Unit Delay Enabled block continue to work for backward compatibility.

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Library

Additional Math & Discrete / Additional Discrete (until R2016b)

Description

The Unit Delay Enabled block delays a signal by one sample period when the external enable signal E is on. While the enable is off, the block is disabled. It holds the current state at the same value and outputs that value. The enable signal is on when E is not 0, and off when E is 0.

You specify the block output for the first sampling period with the value of the Initial condition parameter.

You specify the time between samples with the Sample time parameter. A setting of -1 means that the block inherits the Sample time.

Data Type Support

The Unit Delay Enabled block accepts signals of the following data types:

• Floating point

• Built-in integer

• Fixed point

• Boolean

• Enumerated

The output has the same data type as the input u. For enumerated signals, the Initial condition must be of the same enumerated type as the input u.

For more information, see Data Types Supported by Simulink in the Simulink^® documentation.

Parameters

Initial condition

Specify the initial output of the simulation.

Sample time

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time in the online documentation for more information.

Characteristics

Data Types	Double | Single | Boolean | Base Integer | Fixed-Point | Enumerated
Sample Time	Specified in the Sample time parameter
Direct Feedthrough	No
Multidimensional Signals	No
Variable-Size Signals	No
Zero-Crossing Detection	No
Code Generation	Yes

HDL Code Generation Support

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic. For HDL code generation, it is recommended that you use the Unit Delay Enabled Synchronous (HDL Coder) block instead. This block uses the Unit Delay Enabled with the State Control (HDL Coder) block for synchronous hardware simulation behavior.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline (HDL Coder).
SoftReset	Specify on to generate reset logic for the block that is more efficient for synthesis, but does not match the Simulink behavior. The default is off. See SoftReset (HDL Coder).