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Design and Simulate SerDes Systems

Design and simulate SerDes systems using the SerDes Designer app

High-speed electronic systems suffer from signal degradation caused by various impairments such as impedance mismatch, attenuation, and crosstalk. Using the equalization and gain modulation blocks in the SerDes Toolbox™, you can compensate for the distortions introduced by the lossy channels.

Starting with the SerDes Designer app, you can design the top-level SerDes systems and perform statistical analysis. Use the building blocks and system objects to design, configure, simulate and analyze the SerDes system including the transmitter and the receiver.

Apps

SerDes DesignerDesign and analyze SerDes systems for export to Simulink, MATLAB and IBIS-AMI (Since R2019a)
S-Parameter FitterConvert S-Parameter network to impulse response (Since R2021b)
CTLE FitterFit poles and zeros to CTLE transfer functions (Since R2022a)

Blocks

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DFECDRDecision feedback equalizer (DFE) with clock and data recovery (CDR) (Since R2019a)
CDRModels a clock data recovery circuit (Since R2019a)
DFEClkFwdDFE with Clock Forwarding in the receiver AMI model (Since R2023b)
FFEModels a feed-forward equalizer (Since R2019a)
CTLEModels continuous time linear equalizer (CTLE) (Since R2019a)
AGCAutomatically adjusts gain to maintain output waveform amplitude (Since R2019a)
VGAModels a variable gain amplifier (Since R2019a)
SaturatingAmplifierModels a saturation amplifier (Since R2019a)
IBIS-AMI clock_timesRecover SerDes clock time values from custom DFECDR and CDR (Since R2020b)
PassThroughPropagates baseband signal without modification (Since R2019a)
ConfigurationConfigure system wide settings in SerDes system model (Since R2019a)
StimulusSet waveform generation method and number of symbols to simulate in SerDes model (Since R2019a)
Analog ChannelConstruct loss model from channel loss metric or impulse response (Since R2019a)
AMICo-design SerDes architecture with other vendor designs (Since R2023b)
TxTransmitter block with default settings (Since R2023b)
RxReceiver block with default settings (Since R2023b)
Eye Diagram ScopeDisplay eye diagram of time-domain signal (Since R2023b)

Objects

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serdes.DFECDRDecision feedback equalizer (DFE) with clock and data recovery (CDR) (Since R2019a)
serdes.DFEMinimize intersymbol interference (ISI) at clock sampling times (Since R2023a)
serdes.CDRPerforms clock data recovery function (Since R2019a)
serdes.FFEModels a feed-forward equalizer (Since R2019a)
serdes.CTLEContinuous time linear equalizer (CTLE) or peaking filter (Since R2019a)
serdes.AGCAutomatically adjusts gain to maintain output waveform amplitude (Since R2019a)
serdes.VGAModels a variable gain amplifier (Since R2019a)
serdes.SaturatingAmplifierModels a saturating amplifier (Since R2019a)
serdes.PassThroughPropagates baseband signal without modification (Since R2019a)
serdes.ChannelLossCreate simple lossy transmission line model (Since R2019a)
serdes.StimulusSet a pseudorandom binary sequence (PRBS) pattern and number of symbols to simulate in SerDes model (Since R2021b)
SParameterChannelConvert S-parameter to impulse response (Since R2021a)

Functions

optPulseMetricPulse response metric for optimization routines (Since R2020a)
prbsPseudorandom binary sequence (Since R2020a)
impulse2stepStep response from impulse response (Since R2020a)
impulse2pulsePulse response from impulse response (Since R2020a)
step2impulseImpulse response from step response (Since R2021b)
pulse2impulseImpulse response from pulse response (Since R2020a)
pulse2stateyeStatistical eye from pulse response (Since R2020a)
pulse2pdaPeak distortion analysis eye from pulse response (Since R2020a)
pulse2waveData pattern waveform from pulse response (Since R2020a)
wave2pulsePulse response from data pattern waveform (Since R2020a)

Topics