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Get Started with SerDes Toolbox

Design SerDes systems and generate IBIS-AMI models for high-speed digital interconnects

SerDes Toolbox™ provides a MATLAB® and Simulink® model library and a set of analysis tools and apps for the design and verification of serializer/deserializer (SerDes) systems or high-speed memory PHYs such as DDR5.

With the SerDes Designer app, you can use statistical analysis to rapidly design wired communications links. The app provides parameterized models and algorithms that let you explore a wide range of equalizer configurations to improve channel performance. You can assess metrics such as eye diagram, bathtub curve, and channel operating margin (COM), including the effects of jitter and crosstalk.

With MATLAB based building blocks such as CTLE, DFE, FFE, and CDR, you can describe your chosen architecture using datasheets or measurement data and simulate control and adaptive algorithms. White-box examples of typical applications such as PCIe, USB, Ethernet, and DDR provide reference designs that you can use as a basis for your own designs.

SerDes Toolbox supports automatic generation of dual IBIS-AMI models for statistical analysis and time-domain simulation. These models can be used with third-party channel simulators for system integration and verification.

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