Simulation Speed Improvement Tips
Obtaining Baseline Performance Numbers
You can baseline the performance numbers by timing the execution of the HDL and the Simulink® model separately and adding them together; you may not expect better performance than that. Make sure that the separate simulations are representative: running an HDL-only simulator with unrealistic input stimulus could be much faster than when realistic input stimulus is provided.
Analyzing Simulation Performance
While cosimulation entails a certain amount of overhead, sometimes the HDL simulation itself also slows performance. Ask yourself these questions when trying to analyze and improve performance:
|Consideration||Suggestions for Improving Speed|
|Are you are using NFS or other remote file systems?||How fast is the file system? Consider using a different type or expect that the file system you're using will impact performance.|
|Are you using separate machines for Simulink and the HDL simulator?||How fast is the network? Wait until the network is quieter or contact your system administrator for advice on improving the connection.|
|Are you using the same machine for Simulink and the HDL simulator?||
|Are you using optimal (that is, as large as possible) Simulink sample rates on the HDL Cosimulation block?|
For example, if you set the output sample rate to 1 but only use every 10th sample, you could make the rate 10 and reduce the traffic between Simulink and the HDL simulator.
Another example is if you place a very fast clock as an input to the HDL Cosimulation block, but have none of the other inputs need such a fast rate. In that case, you should generate the clock in HDL or (Xcelium™ and ModelSim® users only) via the Clocks or Simulation pane on the HDL Cosimulation block.
|ModelSim users: Are you compiling/elaborating the HDL using the
Are you using Simulink Accelerator™ mode?
|Acceleration mode can speed up the execution of your model. See "Accelerating Models” in the Simulink User's Guide.|
|If you have the Communications Toolbox™ software, have you considered using Framed signals?||Framed signals reduce the number of Simulink/HDL interactions.|
Cosimulating Frame-Based Signals with Simulink
Overview to Cosimulation with Frame-Based Signals
Frame-based processing can improve the computational time of your Simulink models, because multiple samples can be processed at once. Use of frame-based signals also lets you simulate the behavior of frame-based systems more realistically. The HDL Simulator block supports processing of single-channel frame-based signals.
A frame of data is a collection of sequential samples from a single channel or multiple channels. One frame of a single-channel signal is represented by a M-by-1 column vector. A signal is frame based if it is propagated through a model one frame at a time.
Frame-based processing requires the DSP System Toolbox™ software. Source blocks from the Sources library let you specify a frame-based signal by setting the Samples per frame block parameter. Most other signal processing blocks preserve the frame status of an input signal. You can use the Buffer block to buffer a sequence of samples into frames.
See “Working with Signals” in the DSP System Toolbox documentation for detailed information about frame-based processing.
Using Frame-Based Processing
You do not need to configure the HDL Simulator block in any special way for frame-based processing. To use frame-based processing in a cosimulation, connect one or more single-channel frame-based signals to one or more input ports of the HDL Simulator block. All such signals must meet the requirements described in Frame-Based Processing Requirements and Restrictions. The HDL Simulator block configures any outputs for frame-based operation at the suitable frame size.
Use of frame-based signals affects only the Simulink side of the cosimulation. The behavior of the HDL code under simulation in the HDL simulator does not change in any way. Simulink assumes that HDL simulator processing is sample based. Simulink assembles samples acquired from the HDL simulator into frames as required. Conversely, Simulink transmits output data to the HDL simulator in frames, which are unpacked and processed by the HDL simulator one sample at a time.
Frame-Based Processing Requirements and Restrictions
Observe the following restrictions and requirements when connecting frame-based signals in to an HDL Simulator block:
Connection of mixed frame-based and sample-based signals to the same HDL Simulator block is not supported.
Only single-channel frame-based signals can be connected to the HDL Simulator block. Use of multichannel (matrix) frame-based signals is not supported in this release.
All frame-based signals connected to the HDL Simulator block must have the same frame size.
Frame-based processing in the Simulink model is transparent to the operation of the HDL model under simulation in the HDL simulator. The HDL model is presumed to be sample-based. The following constraint also applies to the HDL model under simulation in the HDL simulator:
|Specify VHDL® signals as scalars values, not vectors or arrays (with the exception of bit vectors. VHDL and Verilog® bit vectors are converted to the suitably-sized fixed-point scalar data type by the HDL Cosimulation block).|
Frame-Based Cosimulation Example
This example shows the use of the HDL Simulator block to cosimulate a VHDL implementation of a simple lowpass filter. In the example, you will compare the performance of the simulation using frame-based and sample-based signals.
This tutorial is specific to ModelSim users; however, much of the process will be the same for Xcelium users.
The example files are (in
The example model:
VHDL code for the filter to be cosimulated:
The filter was designed with Filter Designer and the code was generated by the Filter Design HDL Coder™.
The example uses the data file
as an input signal. This file contains a speech signal. The sample data is of
double, sampled at a rate of 8 kHz.
The next figure shows the
Audio Source Signal From Workspace block provides an
input signal from the workspace variable
mtlb. The block is
configured for an 8 kHz sample rate, with a frame size of 80, as shown in this
The sample rate and frame size of the input signal propagate throughout the model.
The VHDL code file
lp_fir_8k.vhd implements a simple
lowpass FIR filter with a cutoff frequency of 1500 Hz. The HDL
Simulator block simulates this HDL module. The HDL
Simulator block ports and clock signal are configured to match the
corresponding signals on the VHDL entity.
For the ModelSim simulation to execute as we want it to, the
clk_enable signal of the
entity must be forced high. The signal is forced by a pre-simulation command
transmitted by the HDL Simulator block. The command has been
entered into the Simulation pane of the HDL
Simulator block, as shown in the following figure (example shown for
use with ModelSim).
The HDL Simulator block returns output in the workspace
audiobuff1 via the
Filtered Signal To
To run the cosimulation, perform the following steps:
Start MATLAB® and make it your active window.
Set up and change to a writable working folder that is outside the context of your MATLAB installation folder.
Add the example folder to the MATLAB path:
Copy the VHDL file
lp_fir_8k.vhdto your working folder.
Open the example model.
Load the source speech signal, which will be filtered, into the MATLAB workspace.
If you have a compatible sound card, you can play back the source signal by typing the following commands at the MATLAB command prompt:
a = audioplayer(mtlb,8000); play(a);
Start ModelSim by typing the following command at the MATLAB command prompt:
The ModelSim window should now be active. If not, start it.
At the ModelSim prompt, create a design library, and compile the VHDL filter code from the source file
lp_fir_8k.vhd, by typing the following commands:
vlib work vmap work work vcom lp_fir_8k.vhd
The lowpass filter to be simulated is defined as the entity
lp_fir_8k. At the ModelSim prompt, load the instantiated entity
ModelSim is now set up for cosimulation.
Start MATLAB. Run a simulation and measure elapsed time as follows:
tic; sim(gcs); toc Elapsed time is 2.7190 seconds.
The timing in this code excerpt is typical for a run of this model given a simulation Stop time of 1 second and a frame size of 80 samples. Timings are system-dependent and will vary slightly from one simulation run to the next.
Take note of the timing you obtained. For the next simulation run, you will change the model to sample-based operation and obtain a comparative timing.
MATLAB stores the filtered audio signal returned from ModelSim in the workspace variable
audiobuff1. If you have a compatible sound card, you can play back the filtered signal to hear the effect of the lowpass filter. Play the signal by typing the following commands at the MATLAB command prompt:
b = audioplayer(audiobuff1,8000); play(b);
Open the block parameters dialog box of the
Audio Source Signal From Workspaceblock and set the Samples per frame property to
1, as shown in this figure.
Close the dialog box, and select the Simulink window. On the Modeling tab, in the Compile section, click Update Model.
Now the source signal (and all signals inheriting from it) is a scalar.
Start ModelSim. At the ModelSim prompt, type
Start MATLAB. Run a simulation and measure elapsed time as follows:
tic; sim(gcs); toc Elapsed time is 3.8440 seconds.
Observe that the elapsed time has increased significantly with a sample-based input signal. The timing in this code excerpt is typical for a sample-based run of this model given a simulation Stop time of 1 second. Timings are system-dependent and will vary slightly from one simulation run to the next.
Close down the simulation in an orderly way. In ModelSim, stop the simulation by selecting Simulate > End Simulation, and quit ModelSim. Then, close the Simulink model window.