Main Content

Automatic Verification of Generated HDL Code from MATLAB

The automatic verification feature integrates verification as part of the workflow for HDL cosimulation using the HDL Workflow Advisor. During this workflow, MATLAB® generates a test bench for HDL cosimulation. This test bench compares the generated HDL DUT outputs (from the generated hdlverifier.HDLCosimulation System object™) with the original MATLAB function outputs. This step automatically runs this test bench and returns pass/fail information. If the outputs of the HDL DUT match the output of the original MATLAB function in the test bench, the test passes.

This feature requires an HDL Coder™ and an HDL Verifier™ license.

  1. Start the MATLAB HDL Workflow Advisor.

  2. Expand HDL Verification on the left pane and click Verify with Cosimulation.

  3. Select Generate HDL test bench to instruct HDL Coder to generate HDL test bench code from your MATLAB test script (optional).

  4. Select Log outputs for comparison plots if you would like to log and plot outputs of the reference design function and HDL simulator (optional).

  5. For Cosimulate for use with, select Mentor Graphics ModelSim, Cadence Incisive, or Xilinx Vivado Simulator as the HDL simulator you want for cosimulation.

  6. For HDL simulator run mode in cosimulation, select Batch mode for non-interactive simulation. Select GUI mode to view waveforms (not available for cosimulation with Vivado®).

  7. Select Simulate generated cosimulation test bench to automatically verify the generated HDL code in a cosimulation test bench.

  8. For Advanced Options, select and set the optional parameters according to the descriptions in the following table.

    Clock high time (ns)Specify the number of nanoseconds the clock is high.
    Clock low time (ns)Specify the number of nanoseconds the clock is low.
    Hold time (ns)Specify the hold time for input signals and forced reset signals.
    Clock enable delay (in clock cycles)Specify time (in clock cycles) between deassertion of reset and assertion of clock enable.
    Reset length (in clock cycles)Specify time (in clock cycles) between assertion and deassertion of reset.
  9. Optionally, select Skip this step if you don’t want to verify with cosimulation.

  10. Click Run.

    If you selected Batch mode, a command window appears to launch the HDL simulator and run the cosimulation. This window is closed programmatically. If you selected GUI mode, the HDL simulator is opened and left open after simulation so that you may examine the waveforms and other signal data.

    If there are errors, those messages appear in the message pane. Correct any errors and click Run.