Perform Logic Synthesis Using Design Compiler

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This example shows how to generate HDL code for a Simulink® model and run logic synthesis by using Synopsys® Design Compiler in the HDL Workflow Advisor.

Prerequisites

To run this example, you must install:

  • Synopsys® Design Compiler 2024.09

  • Use MATLAB installed on a Red Hat Linux operating system.

Set Synthesis Tool Paths

HDL Workflow Advisor invokes third‑party tools during the synthesis and implementation tasks. Use hdlsetuptoolpath to add the supported tool to the system path and set up environment variables for the current MATLAB session.

To set the Design Compiler tool path, enter:

hdlsetuptoolpath("ToolName","Design Compiler","ToolPath",... installation­_path);

Where installation­_path is the path to the Design Compiler installation.

Open Model

Open the hdlcoder_led_blinking model, which is compatible for HDL code generation. At the MATLAB command prompt, enter:

open_system("hdlcoder_led_blinking");

Generate HDL Code

Next, specify the workflow, select synthesis tool, check the model readiness, and generate RTL code.

1. Open HDL Workflow Advisor. In the Simulink Toolstrip, select Apps > HDL Coder. In the HDL Coder tab, click Workflow Advisor.

2. In the HDL Workflow Advisor, in task 1.1. Set Target Device and Synthesis Tool:

  • Set Target workflow to Generic ASIC/FPGA.

  • Set Synthesis Tool to Design Compiler.

  • Click Run This Task.

Configuring target device and synthesis tool in HDL Workflow Advisor

3. In task 1.2. Set Target Frequency, set Target frequency (MHz) to 50. For more information, see Target Frequency.

4. In task 2.1. Check Model Settings, click the HDL Code Advisor to run additional compatibility checks, and then click Run This Task.

5. In task 3.1 Set HDL Options, set HDL code generation options using the HDL Code Generation Settings. For example, to customize the target HDL language and the target code generation folder, use the Set HDL Options task. After making changes, click Apply.

6. In the task 3.2. Generate RTL Code and Testbench, select Generate RTL code and Generate test bench, and then click Run This Task.

Perform Logic Synthesis Using Design Compiler

Next, create a Design Compiler project and synthesize the generated HDL code.

1. In task 4.1. Create Project, set Synthesis workflow to Default. When you select default synthesis workflow, the Setup Tcl file, Constraints Sdc files and Synthesis Tcl file options are dimmed.

2. Click Run This Task.

The Result pane displays the status and links to the generated log file and Tcl file.

Step 4 Create project in HDL Workflow Advisor

3. In task 4.2.1 Run Synthesis, choose how to run the synthesis:

  • Clear Run build process externally to run synthesis process inside HDL Workflow Advisor. If you choose this option, MATLAB is unavailable until the synthesis completes.

  • Select Run build process externally to run synthesis process in an external console. If you choose this option, you can continue to use MATLAB while the synthesis completes.

4. Click Run This Task.

The Result pane displays the synthesis status and links to the log file and outputs.

Perform logic synthesis, Run build process externally is selected

When you select Run build process externally, the task 4.2.1 completes and the results are displayed in the external window.

Use Custom synthesis Settings

To synthesize HDL code by using custom settings, in task 4.1 Create Project, set the Synthesis workflow to Custom. Then specify the Setup Tcl file, Constraints Sdc files and Synthesis Tcl file parameters, and perform the steps 2 through 4.

See Also

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