Generate VHDL or SystemVerilog code for model references into a single library

Code placement for model references

Model Configuration Pane: Global Settings / General

Description

Specify whether VHDL^® or SystemVerilog code generated for model references is in a single library, or in separate libraries.

This option is enabled when the target language (specified by the Language option) is VHDL or SystemVerilog.

off (default) | on

Default: Off

on: Generate VHDL or SystemVerilog code for model references into a single library.
off: For each model reference, generate a separate VHDL or SystemVerilog library.

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example:

Pass the property as an argument to the makehdl function.
```
makehdl(gcb,'UseSingleLibrary','on')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param(gcs,'UseSingleLibrary','on')
makehdl('myDUT')
```

No recommended settings.

Parameter: UseSingleLibrary

Type: character vector

Value: 'on' | 'off'

Default: 'off'

Introduced in R2015a