Achieving STARC and DO-254 Compliance Using HDL Coder Generated Code

By Kiran Kintali, MathWorks

This article explains how to achieve compliance with Semiconductor Technology Academic Research Center (STARC) design style guides and the DO-254 standard using HDL Coder™ and Model-Based Design. HDL Coder generates target-independent, synthesizable Verilog® and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code is bit-true and cycle-accurate to source designs, and can be targeted to FPGAs and ASICs for both prototyping and production.

The article outlines major steps involved in generating standards-compliant ASIC and FPGA designs using HDL Coder, and explains how HDL Coder features can be used to enhance and facilitate critical stages of compliance testing in a hardware design workflow.

This article was published in EDN Network.

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Published 2014


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