Steven

McMaster University

2011 年からアクティブ

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質問

HDL Coder generates 'real' types - how to prevent that
Hello, I am generating a large system into VHDL code using the HDL Coder. A lot of the signal types are inherited or allows M...

14年以上前 | 2 件の回答 | 0

2

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質問

Unit Delay can't resolve discrete time
Hello, All my unit delay blocks in my current model is getting this error when I run the HDL coder: "Cannot find valid sam...

14年以上前 | 1 件の回答 | 0

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質問

Simulink to VHDL using VHDL Coder but "Data Type Conversion" blocks don't compile
Hello, I have a simulink model that compiles and runs perfectly fine in Simulink. The model has several Data Type Conversion ...

14年以上前 | 2 件の回答 | 0

2

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質問

Simulink 'x' bit shifter - serial to parallel
Hello, My inputs into my model all come from I/O pins serially. Therefore, I need to create a serial to parallel block to be ...

14年以上前 | 1 件の回答 | 0

1

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質問

Tolerances on Simulink Blocks
I want to be able to specify exact tolerances on Simulink Blocks. I want to be able to specify more than just the min/max. I nee...

14年以上前 | 1 件の回答 | 0

1

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質問

Simulink Fixed Point Advisor
I recently got Simulink fixed point toolbox and I opened up my project and it opened fine the first time. I did a couple changes...

14年以上前 | 1 件の回答 | 0

1

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