luckfy zhang

2018 年からアクティブ

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How can I figure out how many delay units do I need in one part of Simulink HDL design?
Hi, Recently, I am interested in debuging your ZYNQ hwswcodesign model. The figure below is one part of Rx Data decoding bl...

5年以上前 | 1 件の回答 | 0

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How can I migrate MathWorks support on ZedBoard to Xilinx ZC702 board?
Hello, everyone: I have noticed MathWorks support on ZYNQ and AD9361 series algorithm development. All these tutorials are ...

5年以上前 | 1 件の回答 | 0

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Where can I set output and input port of an HDL-supported Simulink model?
I am using a Simulink model commqpsktxhdl. I have managed to output HDL code and I found that there 3 inputs including clk, clk-...

6年以上前 | 1 件の回答 | 0

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In simulink, Why does output datatype does not match to my settings?
Hello, everyone. I am using Xilinx System generator in the environment of Simulink. As you can see, I want to use a parallel...

6年以上前 | 0 件の回答 | 0

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