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Bharathi Yogaraj

2021 年からアクティブ

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I'm a development manager at MathWorks , focusing on deep learning deployment on FPGA and vision application

Programming Languages:
VHDL
Spoken Languages:
English

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Seeking Guidance on Auto-Generating Verilog Code for ASIC Simulation with HDL Coder and Deep Learning HDL Toolbox
After creating hPC, use the following commands to generate verilog code for ASIC workflow that is independent of any specific ve...

4ヶ月 前 | 1

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Latency for NN deployment information using DL HDL toolbox
When the activation layers are placed after the convolution or fully connected layers, they are fused together to avoid any extr...

1年以上 前 | 0

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Deep Learning toolbox commands sent
In above script, Instructions will be generated for specified network(net) and specified bitstream('zcu102_single') using hW.c...

1年以上 前 | 0

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Can Deep learning HDL toolbox be used for a customized FPGA board without DDR memory?
Below example shows how to create custom board and generate a deep learning processor IP core for the custom board. https://ww...

1年以上 前 | 0

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Fog rectification reference algorithm
Here are references for Fog rectification example: 1. He, Kaiming. "Single Image Haze Removal Using Dark Channel Prior." Thesis...

2年以上 前 | 0

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Hardware platform for "Stereo Disparity using Semi-Global Block Matching" example
Currently, output frame is reconstructed only based on valid signal. The algorithm does not consider back & front porch during p...

4年弱 前 | 1