HDL Coder Support Package for Xilinx RFSoC Devices

Generate code for the FPGA portion of RFSoC devices

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更新 2022/9/14

This support package includes reference designs for popular RFSoC development kits, so you can generate HDL code and port mappings to I/O and AXI registers to interface with RF tiles and DDR memory, and interactively control the FPGA design from MATLAB.

You can use SoC Blockset for system-level modeling of RFSoC devices, configuration of custom RFSoC-based boards, and deployment of complete SoC applications, including executables for ARM Cortex-A53 processors.

This support package is functional for R2021a and beyond.

For R2021a, to access the documentation for this support package, use the following commands in MATLAB:
>>cd(hdlcoder_rfsoc_doc_root)
>>open('hdlcoder_rfsoc_support_package_doc.pdf')

MATLAB リリースの互換性
作成: R2021a
R2021a 以降 R2022b 以前と互換性あり
プラットフォームの互換性
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ヒントを与えたファイル: Avnet RFSoC Explorer

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