HDL Verifier Self-Guided Tutorial

Learn how to verify an algorithm on FPGAs using MATLAB and Simulink.

HDL Verifier™ enables you to reuse your system-level design environment in your HDL design environment. You can test and verify RTL designs against golden reference models in MATLAB® and Simulink®, debug designs in third-party simulators or hardware, and generate testbenches and verification IP.

This tutorial is designed to help you learn about three of the most popular features of HDL Verifier: HDL Cosimulation, FPGA-in-the-Loop, and FPGA Data Capture. The tutorial shows you how you can use these features whether you develop HDL on your own or use HDL Coder™ to generate HDL from MATLAB or Simulink.

Contents

The Tutorial provides instructions to run HDL Cosimulation with MATLAB and Simulink, perform FPGA validation using FPGA-in-the-Loop simulation, and load signals from designs programmed into development boards into MATLAB using FPGA Data Capture. The tutorial has the following sections.

HDL Cosimulation with Simulink

• Cosimulation with existing HDL code (i.e., hand-coded RTL workflow)
• Cosimulation with HDL code generated by HDL Coder

FPGA-in-the-loop (FIL) with Simulink

• FPGA-in-the-Loop simulation with existing HDL code (i.e., hand-coded RTL workflow)
• FPGA-in-the-Loop simulation with HDL code generated by HDL Coder

FPGA Data Capture

• Data capture for existing HDL code (i.e., hand-coded RTL workflow)
• IP core generation workflow that integrates FPGA Data Capture as part of IP core generation in an existing AXI Stream project

Examples are provided throughout the guide to illustrate concepts