- Reduce the number of IOs your design requires
- Target a chip that has more IO pins
Error in generated HDL code...
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Hi ... I am generating HDL code for the generation of FMCW signal .but error comes as follows. Here i attached the test model for your reference.
ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device. ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed.
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Tim McBrayer
2013 年 10 月 24 日
編集済み: Tim McBrayer
2013 年 10 月 24 日
This has nothing to do directly with MathWorks products. There is no error in the generated code. Your HDL design simply has too many primary I/O ports for the device you are targeting. The two obvious approaches are:
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