FPGA in the Loop minimum clock frequency
1 回表示 (過去 30 日間)
古いコメントを表示
I want to do an FPGA simulation with a small clock frequency. However filWizard does not allow to give smaller than 5MHz to the design. How to achieve this? Thanks.
0 件のコメント
回答 (1 件)
Madhu Varshini
2022 年 6 月 14 日
To get FPGA simulation with a small clock frequency, try increasing oversampling factor of the design. The Oversampling factor delays output, thereby clock frequency can go low.
You can refer the following link for more detail about target frequency:
You can refer the following link to get more information about FPGA system clock frequency, you can refer the following link:
You can refer the following link to get more detail about relation between sampling frequency, FPGA clock frequency and oversampling factor, you can refer the following link.
0 件のコメント
参考
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!