Solver error in HDL verifier

Hi there,

I'm trying to verify my VHDL code with HDL Verifier. I used the cosimWizard to generate the ModelSim Simulator block. When I try to start the Simulink simulation the following error appears:

The "VariableStepDiscrete" solver cannot be used to simulate block diagram 'control' because it contains continuous states

I tried to change the solver to FixedStepDiscrete but no way, same error.

Since the VHDL block I'm implementing is inherently discrete, why the solver give me such an error?

Thanks in advance.

Answer 1

[stozaki]

When you generate and simulation to use the HDL coder, SolverType must set Fixed-Step.

Please see following URL

HDL Coder currently supports variable-step solvers under limited conditions. See hdlsetup

It is reasonable for you to use the hdlsetup function.

[Giuseppe Galioto]

I have not generated my code with HDL Coder. I have written my own VHDL code and I'm usign HDL Verifier to test it in SImulink.

I tried with FixedStep Discrete Solver but it gives me the same error.

[stozaki]

The solver affects when running a simulation. This setting is valid for code generation and simulation (include co-simulation).

[stozaki]

MathWorks provide modeling guideline for HDL coder. It says that Fixed Step Discrete Solver is recommended.

https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide