Axi stream interface in Xilinx system generator
1 回表示 (過去 30 日間)
古いコメントを表示
Hello there, I am trying to implement the AXI stream interface to an image negative operation in system generator. I want to verify whether my design is correct to export as an IP, in terms of enabling the bus signals. (in simulation its working fine) thanks in advance.
0 件のコメント
回答 (0 件)
参考
カテゴリ
Help Center および File Exchange で Communications Toolbox についてさらに検索
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!