HDL Counter implementation issues with Zedboard

Hi,

I am trying to run a simple HDL counter in simulink with word lenght 8, unsigned. The sample time is set to 1us in simulink. The program excutes perfectly in normal mode.

I am using HDL workflow advisor to program this counter into Zedboard. The output of the counter is connected to I/O pin (PMOD JA1 connector) and is read back in simulink. Upon implementating this program into Zedboard, I see that the 0th bit of the counter is at 25MHz, however, intented was 1MHz (sampling time =1us). And the read back through AXI4-Lite in simulation shows random steps.

I am not able to get the clk rate that I desire in the hardware implementation. Here I plan to have 1us (1MHz), however, I get 40ns (25MHz). Can some one please clarify the sampling time in simulink and correlation with hardware implementation.

I am using MATLAB 2014a with support packages for ZYNQ 7000 and Vivado 2013.4.

Best Regards, Anirudh