How to generate a parallel input interface (or vector port) using HDL Coder

Hi,

The input interface of my module is designed as a parallel bus (e.g., [1023:0], [31:0] data1, [63:32] data2). However, HDL Coder separates this parallel port into individual scalar ports, which is incompatible with my system architecture. How can I configure HDL Coder to generate packed vector ports instead of individual ports?

Looking forward to your kindly reply.

Answer 1

[Umar]

Hi @KH,

What you're seeing is expected behavior, and there's a setting that controls it, though it works differently depending on which HDL language you're generating.

If you're generating VHDL, go to Configuration Parameters, then HDL Code Generation, then Global Settings, then the Ports tab, and set "Scalarize Ports" to off. That should keep your bus packed as a single vector instead of being split into individual scalar signals. You can also do this from the command line with hdlset_param(modelname, 'ScalarizePorts', 'off').

If you're generating Verilog, this is where it gets tricky. Verilog output gets flattened into scalar ports by default no matter what you set ScalarizePorts to. That's just a hard limitation in HDL Coder right now, not something you can configure your way around.

So depending on your toolchain, you have a couple of realistic options: One, switch your target language to VHDL and turn scalarization off, if your downstream tools can work with VHDL instead of Verilog.

Two, if you're stuck with Verilog, let HDL Coder generate the scalarized ports as it normally would, then write a small wrapper module around the generated DUT that packs and unpacks the wide bus at the boundary. So your system still sees one clean 1023:0 style port, and the wrapper handles splitting it into the individual signals HDL Coder actually generated underneath.

It's also worth checking whether you're modeling this using a proper bus object with named elements like data1 and data2, versus a plain vector signal, since HDL Coder can treat those a bit differently in terms of preserving structure. Here's the MathWorks documentation page that covers this in detail, including the model example they walk through:

https://www.mathworks.com/help/hdlcoder/ug/scalarization-of-vector-ports.html

Hope this helps!