How is SoC Blockset working with Cortex-R5 processor on ZCU111?

Dear all,

I am using SoC Blockset to design applications for AMD Zynq Ultrascale+ ZCU111 evaulation board, which has a hardware support package from MathWorks.

The board features two processors:

1) Quad-core ARM Cortex-A53

2) Dual-core ARM Cortex-R5

SoC Blockset offers possibility to design an application for the processing system of the board, for which code is then generated and the application is deployed. As I understand this only applies to A53 running with firmware from MathWorks which is downloaded to the SD card during hardware setup for "SoC Blockset support package for AMD FPGA and SoC devices". However, I have not found any information about how matlab works with R5 at all. For example if I connect to the board using PuTTy, I can see the information about 4 cores, which indicates that I am connected to A53.

Am I correct that the processor model is deployed on A53? Does SoC Blockset workflow allow to make use of R5 processor? What is the purpose of R5 at all?

Thank you!

Answer 1

[Umar]

Hi @Sergei,

Thank you for your detailed questions. Based on the official MathWorks SoC Blockset documentation and supported hardware listings, here’s a breakdown addressing each of your points:

Deployment on the ARM Cortex-A53

_ You are correct_: the SoC Blockset workflow primarily targets the Cortex-A53 cores of the Zynq UltraScale+ MPSoC ZCU111 evaluation board. When you generate code and deploy an application using the SoC Blockset support package, the code runs on the A53 cores, and the firmware provided by MathWorks is downloaded to the SD card as part of the setup.

Use of the ARM Cortex-R5 cores

The documentation does not mention support for deploying SoC Blockset-generated applications to the R5 cores. This is consistent with the workflow focus on the A53 processing system. Therefore, you cannot directly use the SoC Blockset to generate and deploy MATLAB applications to the R5 cores.

Purpose of the ARM Cortex-R5 cores

The R5 cores are included in the ZCU111 for real-time, low-latency, or safety-critical tasks. They typically run bare-metal code or an RTOS independently of the A53 cores. These cores are often used for deterministic control loops, sensor interfacing, or other tasks that require real-time execution, separate from the main application running on the A53 cores.

Accessing the R5 cores

If you need to utilize the R5 cores, it must be done outside the standard SoC Blockset workflow. Options include:

• Developing bare-metal code that runs directly on the R5 cores.

• Implementing an RTOS on the R5 cores to manage deterministic real-time tasks.

• Setting up *inter-processor communication (IPC) between A53 and R5 cores to coordinate tasks.

The SoC Blockset itself does not provide direct deployment support for these cores, so any workflow involving the R5 will require manual development and configuration.

References from MathWorks documentation:

• SoC Blockset Supported Hardware

• ZCU111 is listed as a supported Xilinx Zynq UltraScale+ RFSoC device.

• SoC Blockset workflows target the processing system (A53 cores) for code generation.

In summary, your observations are correct: SoC Blockset applications are deployed on the A53 cores, and the R5 cores are available for real-time tasks but require custom programming outside of the SoC Blockset workflow.

[Sergei]

Thank you a lot for your answer!

Everything is clear, one last question:

There is a template for SoC Blockset called "Multiprocessor Architecture template" https://www.mathworks.com/help/soc/ug/multiprocessor-architecture-template.html

As I undertsand this architecture is not applicable in my case, is that so?

Thank you!