Digital Down Converter: # Samples must be Integer multiple of decimation factor

Hello,

I'm trying to simulate a system that receives an analog signal, samples it and performs various filtration and decimation tasks on the input. Essensially it is supposed to mimic a Zynq UltraScale+ operation.

The current system blocks look like this:

The model is set at a fixed step size of 250 ps (4 GSa/s). A sinusoidal signal at a frequency of 503.75 MHz enters an RF front end, which adds amplification and noise. This signal is sampled by an ideal 14-bit ADC. It then enters a FIR decimator - up to this point everything works correctly.

Now instead of the FIR decimator I want to put a digital down converter, to convert from 503.75 MHz to 3.75 MHz, and apply a FIR decimator. All in one DDC block.

However, the DDC doesn't want to run. Whatever I do, it outputs the following error:

The number of rows in the input signal must be an integer multiple of the total decimation factor: 40.

I have added an output to workspace which clearly shows that the time vector is 4000 samples long. It is a multiple of 40.

I have tried changing the decimation factor to anything between 2 and 20, but nothing works. What am I missing?

The parameters of the DDC block are as follows (I have tried specifiying the input sample rate at 4 GHz - doesn't help):

[Fangjun Jiang]

Double click the DDC block, click Help, take a look at the example model.

[Egor Losev]

I did. The example model doesn't run and not all setttings, such as property editor, are accessible.

Fine, I deduced that I need to set a subsystem and designate the domain as dataflow. I set the frame size to automatic

Now I get this error:

Insert a Buffer block before input port 1.

I insert a buffer before input port 1 (input to DDC), even through its not in the example model.

Now I get this:

Error:An error occurred in the block 'GenericADC/Subsystem' during compile.
Caused by:
    Insufficient number of outputs from right hand side of equal sign to satisfy assignment.

This is the same error I was getting from the example model, which doesn't run.

[Fangjun Jiang]

Not sure why. In R2023b, I run open_system('familyRadioServiceExample') and then was able to simulate the model.

check if you have the latest update. MATLAB Version: 23.2.0.2515942 (R2023b) Update 7

In MATLAB, click Help, Check for Updates.

[Egor Losev]

Fully reinstalled MATLAB, updated to the latest version.

Still, when I open this example and run it I get the same error:

Error:An error occurred in the block 'familyRadioServiceExample/Dataflow Subsystem/Resample to 50 KHz' during compile.
Caused by:
    Insufficient number of outputs from right hand side of equal sign to satisfy assignment.

[Fangjun Jiang]

contact Mathworks tech support

Answer 1

[Tom Richter]

Hi Egor,

I agree with Fangjun and suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.com/support/contact_us.html, you can submit a support request and add example or reproduction files. The page also displays phone contact information based on your location.

Best regards,

Tom