Simulink automatically generates Verilog. How should it run on FPGA

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wang 2023 年 3 月 21 日

編集済み: wang 2023 年 3 月 21 日

I have generated Verolig from part of the module, how do I run this part of Verilog on the FPGA?

“bufen”This subsystem has generated Verilog.And need to measure the time used to run on FPGA.

I plan to run the original algorithm on MATLAB and only this small part on FPGA.

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