Looking for a way to change Simulink parameters at or after compile time with HDL coder

Using Simulink 2013 and the HDL coder, I'm looking for a way to change model parameters at run-time (like ports) or at compile time (like generics). I know parameters aren't exposed as ports (<http://www.mathworks.com/matlabcentral/answers/114813-can-i-export-simulink-block-parameters-to-the-vhdl-entity-port-list#answer_123251)>, but I'm looking for a way to change them. From what I can tell, the parameter is somewhat optimized-out of the VHDL code when Simulink builds it, even though the parameter name is retained as a buried signal. Maybe there's a way to turn off the optimization so a generic parameter calculation is performed? Then I could manually expose the parameter as a port. We could fall-back on creating explicit inports and calculations in lieu of parameters, but I hope there's a better way.

Thank you for any ideas,

Steve K

Answer 1

[Tim McBrayer]

HDL Coder has a limited capability to generate generic values. These appear as a GENERIC port in VHDL or as a PARAMETER in Verilog. The only values that can appear in this form are currently the value of a Simulink gain or constant block.

To have these values show up as a generic VHDL port:

1. Check the "Generate parameterized HDL code from masked subsystem" setting in HDL Code Generation>Global Settings>Coding style
2. Make the containing subsystem atomic
3. Place a mask on the subsystem
4. Make a tunable parameter on the mask with your generic constant.
5. Set the gain/constant values in the subsystem to use this mask parameter

Answer 2

[Sylvain R.]

Unburying the topic, sorry for that.

What Steve needs, looks like the "ExportedGlobal" storage class of Simulink.Parameters. When such a parameter is defined in the Workspace and used in an HDL-Coder generated model, HDL Coder creates a input port for this parameter (very much in the fashion Embedded Coder does it).

I can't say if this existed with 2013.