P-Channel JFET
P-Channel junction field-effect transistor
Libraries:
Simscape /
Electrical /
Semiconductors & Converters
Description
The P-Channel JFET block uses the Shichman and Hodges equations to represent a P-Channel JFET using a model with the following structure:
G is the transistor gate, D is the transistor drain and S is the transistor source. The drain current, ID, depends on the region of operation and whether the transistor is operating in normal or inverse mode.
In normal mode (–VDS ≥ 0), the block provides the following relationship between the drain current ID and the drain-source voltage VDS.
Region Applicable Range of VGS and VDS Values Corresponding ID Equation Off
–VGS ≤ –Vt0 ID = 0
Linear
0 < –VDS < –VGS + Vt0 ID = βVDS(2(–VGS + Vt0) + VDS)(1 – λVDS)
Saturated
0 < –VGS + Vt0 ≤ –VDS ID = –β (–VGS + Vt0)2 (1 – λVDS)
In inverse mode (–VDS < 0), the block provides the following relationship between the drain current ID and the drain-source voltage VDS.
Region Applicable Range of VGS and VDS Values Corresponding ID Equation Off
–VGD ≤ –Vt0
ID = 0
Linear
0 < VDS < – VGD + Vt0
ID = βVDS(2(–VGD + Vt0) – VDS)(1 + λVDS)
Saturated
0 < –VGD + t0V ≤ VDS
ID = β (–VGD + Vt0)2 (1 + λVDS)
In the preceding equations:
VGS is the gate-source voltage.
VGD is the gate-drain voltage.
Vt0 is the threshold voltage. If you select
Specify using equation parameters directly
for the Parameterization parameter, Vt0 is the Threshold voltage parameter value. Otherwise, the block calculates Vt0 from the datasheet parameters you specify.β is the transconductance parameter. If you select
Specify using equation parameters directly
for the Parameterization parameter, β is the Transconductance parameter parameter value. Otherwise, the block calculates β from the datasheet parameters you specify.λ is the channel-length modulation parameter. If you select
Specify using equation parameters directly
for the Parameterization parameter, λ is the Channel-length modulation parameter value. Otherwise, the block calculates λ from the datasheet parameters you specify.
The currents in each of the diodes satisfy the exponential diode equation
where:
IS is the saturation current. If you select
Specify using equation parameters directly
for the Parameterization parameter, IS is the Saturation current parameter value. Otherwise, the block calculates IS from the datasheet parameters you specify.q is the elementary charge on an electron (1.602176e–19 Coulombs).
k is the Boltzmann constant (1.3806503e–23 J/K).
Tm1 is the measurement temperature. The value comes from the Measurement temperature parameter.
The block models gate junction capacitance as a fixed gate-drain capacitance
CGD and a fixed gate-source capacitance
CGS. If you select Specify using
equation parameters directly
for the Parameterization
parameter, you specify these values directly using the Gate-drain junction
capacitance and Gate-source junction capacitance parameters.
Otherwise, the block derives them from the Input capacitance Ciss and
Reverse transfer capacitance Crss parameter values. The two
parameterizations are related as follows:
CGD = Crss
CGS = Ciss – Crss
Modeling Temperature Dependence
The default behavior is that dependence on temperature is not modeled, and the device is simulated at the temperature for which you provide block parameters. You can optionally include modeling the dependence of the transistor static behavior on temperature during simulation. Temperature dependence of the junction capacitances is not modeled, this being a much smaller effect.
When including temperature dependence, the transistor defining equations remain the same. The measurement temperature value, Tm1, is replaced with the simulation temperature, Ts. The transconductance, β, and the threshold voltage, Vt0, become a function of temperature according to the following equations:
Vt0s = Vt01 + α ( Ts – Tm1)
where:
Tm1 is the temperature at which the transistor parameters are specified, as defined by the Measurement temperature parameter value.
Ts is the simulation temperature.
βTm1 is JFET transconductance at the measurement temperature.
βTs is JFET transconductance at the simulation temperature. This is the transconductance value used in the JFET equations when temperature dependence is modeled.
Vt01 is the threshold voltage at measurement temperature.
Vt0s is the threshold voltage at simulation temperature. This is the threshold voltage value used in the JFET equations when temperature dependence is modeled.
BEX is the mobility temperature exponent. A typical value of BEX is -1.5.
α is the gate threshold voltage temperature coefficient, dVth/dT.
For most JFETS, you can use the default value of -1.5
for
BEX. Some datasheets quote the value for α, but most
typically they provide the temperature dependence for the saturated drain current,
I_dss. Depending on the block parameterization method, you have two ways of
specifying α:
If you parameterize the block from a datasheet, you have to provide I_dss at a second measurement temperature. The block then calculates the value for α based on this data.
If you parameterize by specifying equation parameters, you have to provide the value for α directly.
If you have more data comprising drain current as a function of gate-source voltage for fixed drain-source voltage plotted at more than one temperature, then you can also use Simulink® Design Optimization™ software to help tune the values for α and BEX.
In addition, the saturation current term, IS, in the gate-drain and gate-source current equations depends on temperature
where:
ISTm1 is the saturation current at the measurement temperature.
ISTs is the saturation current at the simulation temperature. This is the saturation current value used in the gate diode equations when temperature dependence is modeled..
EG is the energy gap.
k is the Boltzmann constant (1.3806503e–23 J/K).
XTI is the saturation current temperature exponent.
Similar to α, you have two ways of specifying EG and XTI:
If you parameterize the block from a datasheet, you have to specify the gate reverse current, I_gss, at a second measurement temperature. The block then calculates the value for EG based on this data and assuming a p-n junction nominal value of
3
for XTI.If you parameterize by specifying equation parameters, you have to provide the values for EG and XTI directly. This option gives you most flexibility to match device behavior, for example, if you have a graph of I_gss as a function of temperature. With this data you can use Simulink Design Optimization software to help tune the values for EG and XTI.
Thermal Port
You can expose the thermal port to model the effects of generated heat and device temperature. To expose the thermal port, set the Modeling option parameter to either:
No thermal port
— The block does not contain a thermal port and does not simulate heat generation in the device.Show thermal port
— The block contains a thermal port that allows you to model the heat that conduction losses generate. For numerical efficiency, the thermal state does not affect the electrical behavior of the block.
For more information on using thermal ports and on the Thermal Port parameters, see Simulating Thermal Effects in Semiconductors.
Variables
To set the priority and initial target values for the block variables before simulation, use the Initial Targets section in the block dialog box or Property Inspector. For more information, see Set Priority and Initial Target for Block Variables.
Use nominal values to specify the expected magnitude of a variable in a model. Using system scaling based on nominal values increases the simulation robustness. Nominal values can come from different sources. One of these sources is the Nominal Values section in the block dialog box or Property Inspector. For more information, see System Scaling by Nominal Values.
Plot Basic I-V Characteristics
You can plot the basic I-V characteristics of the P-Channel JFET block without building a complete model. Use the plots to explore the impact of your parameter choices on device characteristics. If you parameterize the block from a datasheet, you can compare your plots to the datasheet to check that you parameterized the block correctly. If you have a complete working model but do not know which manufactured part to use, you can compare your plots to datasheets to help you decide.
To enable this option, set the Modeling option parameter of the
P-Channel JFET block to No thermal port
. To plot the basic
characteristics, right-click the block and select Electrical >
Basic characteristics from the context menu. For more
information about the Basic characteristics option, see Plot Basic I-V Characteristics of Semiconductor Blocks.
Assumptions and Limitations
This block does not allow you to specify initial conditions on the junction capacitances. If you select the Start simulation from steady state option in the Solver Configuration block, the block solves the initial voltages to be consistent with the calculated steady state. Otherwise, voltages are zero at the start of the simulation.
You may need to use nonzero ohmic resistance and junction capacitance values to prevent numerical simulation issues, but the simulation may run faster with these values set to zero.
The block does not account for temperature-dependent effects on the junction capacitances.
When you specify I_dss at a second measurement temperature, it must be quoted for the same working point (that is, the same drain current and gate-source voltage) as for the I_dss value on the Main tab. Inconsistent values for I_dss at the higher temperature will result in unphysical values for α and unrepresentative simulation results.
You may need to tune the value of BEX to replicate the ID-VGS relationship (if available) for a given device. The value of BEX affects whether the ID-VGS curves for different temperatures cross each other, or not, for the ranges of ID and VGS considered.
Ports
Conserving
Parameters
References
[1] H. Shichman and D. A. Hodges, Modeling and simulation of insulated-gate field-effect transistor switching circuits. IEEE J. Solid State Circuits, SC-3, 1968.
[2] G. Massobrio and P. Antognetti. Semiconductor Device Modeling with SPICE. 2nd Edition, McGraw-Hill, 1993. Chapter 2.