SoC Generation Workflows

You can deploy an SoC model on an SoC device by using one of these workflows.

• Use the SoC Builder tool to guide you through the steps required to build hardware and software executables, load them on an SoC device, and execute.

• Use the socExportReferenceDesign function to export a reference design from an SoC model, and then integrate your IP code to the reference design and deploy to an SoC device using the HDL Workflow Advisor tool.

• Use the SoC Model Creator (SoC Blockset Support Package for Xilinx Devices) tool to create an SoC model based on the selected reference design for the supported Xilinx^® RFSoC devices. Use the created model as a template to design and simulate an FPGA algorithm and processor algorithm. Then, use the SoC Builder tool to build and deploy the system on an RFSoC device.

All these workflows require the SoC Blockset™ and HDL Coder™ products.

Use SoC Builder Tool to Deploy SoC Model on SoC Device

If you are authoring an SoC model from scratch using SoC Blockset features, first simulate and refine the model as needed. Then, use the SoC Builder tool to guide you through the workflow of checking, building, loading, and executing your design on an SoC device. For an example of using the SoC Builder tool, see Streaming Data from Hardware to Software.

Use socExportReferenceDesign Function to Deploy SoC Model on SoC Device

If you are authoring an IP core using the HDL Coder custom IP core generation workflow, you can create a custom reference design and integrate the IP core into that design. Use the socExportReferenceDesign function to export a reference design from an SoC Blockset model. For an example of using the socExportReferenceDesign function, see Export Custom Reference Design.

Use SoC Model Creator and SoC Builder Tools to Create and Deploy SoC Model on RFSoC Device

This workflow enables algorithm and system designers to generate an HDL IP core and integrate it into a fixed reference design for rapid prototyping. Select a fixed reference design and configure it to create an SoC model using the SoC Model Creator tool. Edit the created model to include an FPGA algorithm and processor algorithm. Then, either simulate the system or use the SoC Builder tool to generate a bitstream and host I/O model, build a software application, and program the Xilinx RFSoC device. For more information on this workflow, see Support for Fixed Reference Design (SoC Blockset Support Package for Xilinx Devices).

If you are designing an RFSoC application on an RFSoC device and building your application using a fixed reference design, launch the SoC Model Creator tool first. If you are building an application based on the content in the Simulink^® model, you can use the RFSoC Template to get started quickly, or you can create the whole model from scratch.