Terminator

Terminate unconnected output port

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Libraries:
Simulink / Commonly Used Blocks
Simulink / Sinks
HDL Coder / Sinks

Description

Use the Terminator block to cap blocks whose output ports do not connect to other blocks. If you run a simulation with blocks having unconnected output ports, Simulink^® issues warning messages. Using Terminator blocks to cap those blocks helps prevent warning messages.

Examples

Simulation of Bouncing Ball

Uses two models of a bouncing ball to show different approaches to modeling hybrid dynamic systems with Zeno behavior. Zeno behavior is informally characterized by an infinite number of events occurring in a finite time interval for certain hybrid systems. As the ball loses energy, the ball collides with the ground in successively smaller intervals of time.

• Open Model

Model Fault-Tolerant Fuel Control System

Combine Stateflow® and Simulink® capabilities to model hybrid systems. This type of modeling is particularly useful for systems that have numerous possible operational modes based on discrete events. Traditional signal flow is handled in Simulink while changes in control configuration are implemented in Stateflow. The model described in this example represents a fuel control system for a gasoline engine. The system is robust in that it detects individual sensor failures, and the control system is dynamically reconfigured for uninterrupted operation.

• Open Model

Simulate Motion in Six Degrees of Freedom (6DOF)

Model six degrees of freedom (6DOF) in Simulink®. The model in this example replicates the motions experienced by an object or vehicle in model in this example replicates axes of rotation (pitch, roll, and yaw) and three axes of translation (heave, surge, and sway). You can switch between using Euler angles and quaternions to model the equations of motion using the representation parameter of the Variant Subsystem block.

• Open Model

Ports

Input

Port_1 — Input signal

scalar | vector | matrix | n-D array | bus

Use this port to direct signals from output ports that are otherwise unconnected during a simulation. The port accepts real or complex signals of all data types.

Data Types: single | double | half | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | string | Boolean | fixed point | enumerated | bus | image

Block Characteristics

Data Types	Boolean | bus | double | enumerated | fixed point | half | integer | single | string
Direct Feedthrough	no
Multidimensional Signals	yes
Variable-Size Signals	no
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

Architecture	Description
No HDL	Do not generate HDL code for this block.

HDL Block Properties

PreserveUpstreamLogic

Control the removal of unconnected logic. The default is off, which means unconnected logic is not preserved in HDL code. For more details, see PreserveUpstreamLogic (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a