Applications
R2026bImplement radar and wireless communication applications
Use DSP HDL Toolbox™ blocks to implement complex applications such as satellite communication, radio detection and ranging (RADAR), and wireless communication.
Topics
Wireless Communication
- Implement Digital Upconverter for FPGA
Design a digital upconverter (DUC) for LTE on FPGAs. - Implement Digital Downconverter for FPGA
Design a digital downconverter (DDC) for LTE on FPGAs. - WLAN HDL Time and Frequency Synchronization (Wireless HDL Toolbox)
Implement WLAN time- and frequency-synchronization algorithm that is optimized for hardware. - Sample Rate Conversion for an LTE Receiver (Wireless HDL Toolbox)
Implement sample rate converter for LTE receiver front end.
Radar
- Beamscan Direction of Arrival Estimation Using FPGA
Estimate direction of arrival (DOA) by using a beamscan technique suitable for implementation on hardware. - Rectangular Array MVDR Beamformer
Implement a minimum-variance distortionless-response (MVDR) beamformer for a 4x4 rectangular antenna array on FPGA. - FPGA-Based Beamforming in Simulink: Algorithm Design
Develop a beamforming algorithm suitable for implementation on hardware (Part 1). - FPGA-Based Beamforming in Simulink: Code Generation
Generate HDL code for a beamforming algorithm (Part 2). - FPGA-Based Monopulse Technique: Algorithm Design
Develop a monopulse technique to perform digital downconversion on hardware (Part 1). - FPGA-Based Monopulse Technique: Code Generation
Generate HDL code for a monopulse digital downconverter (Part 2). - Pulse-Doppler Radar Using AMD RFSoC Device (SoC Blockset)
Build, simulate, and deploy pulse-Doppler radar system using SoC Blockset™ for AMD on Xilinx® RFSoC device. - Detect and Capture Wideband Radar Signal Using AMD RFSoC Device (SoC Blockset)
Build, simulate, and deploy wideband radar signal detection and capture system using SoC Blockset for AMD on Xilinx RFSoC device. - FPGA-Based Cell-Averaging Constant False Alarm Rate (CA-CFAR) Detector
Design a FPGA implementation-ready CA-CFAR detector. - FPGA-Based Uniform Linear Array MVDR Beamformer
Implement a fixed-point HDL-optimized minimum-variance distortionless-response (MVDR) beamformer for a uniform linear sensor array (ULA).
