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F28P65x Memory Configuration

The memory configuration on F28P65x devices differs slightly from its predecessors. F28P65x devices have five flash banks that you can allocate to either CPU1 or CPU2. Additionally, CPU1 or CLA can use the LS RAM, while RAM Dx memory can be mapped to either CPU1 or CPU2.

Flash Bank Configuration

In the C2000™ Microcontroller Blockset, flash banks 0-2 are assigned to CPU1, and flash banks 3 and 4 are assigned to CPU2.

If you do not configure the banks similarly in the CCS tool, you might encounter the following error when downloading the .out file generated in Simulink externally in the CCS tool. You won't see this error when downloading the code in Simulink:

C28xx_CPU2: Flash Programmer: Error erasing Bank 0 FMSTAT (STATCMD on some devices) value = 65. Operation Cancelled (0). 
C28xx_CPU2: File Loader: Memory write failed: Unknown error 
C28xx_CPU2: GEL: File: <generated .out file>: Load failed.

Configuring Flash Banks in CCS Tool

Follow these steps to configure the flash banks in the CCS tool:

  1. Right-click the ccxml file for the F28P65x device and select Launch Selected Configuration to open the debug view.

  2. In the debug view, select the core C28xx_CPU1 and navigate to Tools > On_Chip Flash to open the CPU1 flash plugin GUI.

  3. In the CPU1 flash plugin GUI, under Flash Bank Map Settings, map Bank 0, 1, and 2 to CPU1 and Bank 3 and 4 to CPU2 as shown in the image.

  4. Navigate to the Erase Settings section in the GUI and enable flash banks 0, 1, and 2 as the banks that the CPU1 flash plugin can erase, as shown in the image.

  5. Navigate to the top of the CPU1 flash plugin GUI and use the Configure Clock button to set up the PLL. Ensure you complete this step before performing any CPU2 flash plugin operations, including loading executables onto CPU2 flash.

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  6. Now, in the debug view, select the core C28xx_CPU2 and navigate to the menu option Tools > On_Chip Flash. This action will open the CPU2 flash plugin GUI.

  7. Similarly to steps 3 and 4, in the CPU2 flash plugin GUI, map Bank 0-2 to CPU1 and map Bank 3 and 4 to CPU2. Additionally, under Erase settings, enable Bank 3 and Bank 4 to allow them to be erased by the flash plugin for CPU2.

  8. To ensure CCS remembers your configured settings in the flash plugin GUI, click on the Remember My Settings button located at the bottom of the GUI. This action will save your settings for future iterations.

RAM D Memory Configuration

The .cmd file shipped for F28P65x devices in C2000 Microcontroller Blockset divides RAM D memory as follows: RAMD0 and RAMD1 are allocated to CPU1, while RAMD2 to RAMD5 are allocated to CPU2.

LS RAM Configuration

The LS RAM memory is exclusively accessible by CPU1 and CLA. You can configure this memory allocation in the model configuration parameters. Navigate to Hardware Implementation > Target hardware resources > Build options and choose Configure CLA program and data memory.

See Also