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PLL (3ph)

Determine frequency and fundamental component of three-phase signal phase angle


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  • PLL (3ph) block


The PLL (3ph) block models a Phase Lock Loop (PLL) closed-loop control system, which tracks the frequency and phase of a sinusoidal three-phase signal by using an internal frequency oscillator. The control system adjusts the internal oscillator frequency to keep the phases difference to 0.

The figure shows the internal diagram of the PLL.

The three-phase input signal is converted to a dq0 rotating frame (Park transform) using the angular speed of an internal oscillator. The quadrature axis of the signal, proportional to the phase difference between the abc signal and the internal oscillator rotating frame, is filtered with a Mean (Variable Frequency) block. A Proportional-Integral-Derivative (PID) controller, with an optional automatic gain control (AGC), keeps the phase difference to 0 by acting on a controlled oscillator. The PID output, corresponding to the angular velocity, is filtered and converted to the frequency, in hertz, which is used by the mean value.


Minimum frequency (Hz)

Specify the minimum expected frequency of the input signal. This parameter sets the buffer size of the Mean (Variable Frequency) block used inside the block to compute the mean value. Default is 45.

Initial inputs [ Phase (degrees), Frequency (Hz) ]

Specify the initial phase and frequency of the input signal. Default is [0, 60].

Regulator gains [ Kp, Ki, Kd ]

Specify the proportional, integral, and derivative gains of the internal PID controller. Use the gains to tune the PLL response time, overshoot, and steady-state error performances. Default is [180, 3200, 1].

Time constant for derivative action (s)

Specify the time constant for the first-order filter of the PID derivative block. Default is 1e-4.

Maximum rate of change of frequency (Hz/s)

Specify the maximum positive and negative slope of the signal frequency. Default is 12.

Filter cut-off frequency for frequency measurement (Hz)

Specify the second-order lowpass filter cut-off frequency. Default is 25.

Sample time

Specify the sample time of the block, in seconds. Set to 0 to implement a continuous block. Default is 0.

Enable automatic gain control

When this check box is selected, the PLL block optimizes its performances by scaling the PID regulator signal according to the input signal magnitude. Select this option when the input signal is not normalized. Default is selected.

Inputs and Outputs


The normalized three-phase signals, in pu.


The measured frequency, in hertz.


Angle (rad) varying between 0 and 2*pi, synchronized on zero crossings of the fundamental (positive-sequence) of phase A.


Sample TimeSpecified in the Sample Time parameter.
Continuous when Sample Time = 0.
Scalar ExpansionNo
Zero-Crossing DetectionYes


The power_PLL example shows the use of the PLL (3ph) and PLL blocks.

The PLL block is fed by a sinusoidal signal of 60 Hz, increasing to 61 Hz from 0.5 s to 1.5 s. Notice that the frequency reaches the new frequency in a short response time.

The PLL (3ph) block is fed by three-phase sinusoidal signals increasing from 60 Hz to 61 Hz between 0.5 and 1.5 seconds. The PLL (3ph) frequency reaches the new frequency faster than the PLL due to the additional phase information.

The model sample time is parameterized with the variable Ts (with a default value of 0). To discretize the PLL block, at the MATLAB® command prompt, enter

Ts = 50e-6

Version History

Introduced in R2013a